i2c_synplify.vhd

Xilinx ISE 官方源代码盘第十章

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_1444 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_1444;

architecture beh of LUT4_1444 is
  signal GND : std_logic ;
  signal VCC : std_logic ;
  signal N_14 : std_logic ;
  signal N_16 : std_logic ;
  signal I0_I : std_logic ;
begin
  N_16 <= I3 and I2 after 100 ps;
  O <= N_14 and I0_I after 100 ps;
  GND <= '0';
  VCC <= '1';
  N_14 <= N_16 xor I1 after 100 ps;
  I0_I <= not I0;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_FFEA is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_FFEA;

architecture beh of LUT4_FFEA is
  signal N_6 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  N_6 <= I2 and I1 after 100 ps;
  O <= N_6 or I3 or I0 after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_88A8 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_88A8;

architecture beh of LUT4_88A8 is
  signal N_6 : std_logic ;
  signal N_7 : std_logic ;
  signal I3_I_0 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  N_7 <= I3_I_0 and I2 after 100 ps;
  N_6 <= N_7 or I1 after 100 ps;
  O <= N_6 and I0 after 100 ps;
  I3_I_0 <= not I3;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_EAC0 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_EAC0;

architecture beh of LUT4_EAC0 is
  signal GND : std_logic ;
  signal VCC : std_logic ;
  signal N_9 : std_logic ;
  signal N_11 : std_logic ;
begin
  N_11 <= I3 and I0 after 100 ps;
  GND <= '0';
  VCC <= '1';
  O <= N_11 or N_9 after 100 ps;
  N_9 <= I2 and I1 after 100 ps;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_101F is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_101F;

architecture beh of LUT4_101F is
  signal N_7 : std_logic ;
  signal I3_I_0 : std_logic ;
  signal I1_I_0 : std_logic ;
  signal I0_I_0 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  N_7 <= I1_I_0 and I0_I_0 after 100 ps;
  O <= I3_I_0 after 100 ps when I2 = '0' else N_7 after 100 ps;
  I3_I_0 <= not I3;
  I1_I_0 <= not I1;
  I0_I_0 <= not I0;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT3_08 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  O :  out std_logic);
end LUT3_08;

architecture beh of LUT3_08 is
  signal I2_I_0 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  I2_I_0 <= not I2;
  O <= I2_I_0 and I1 and I0 after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_F888 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_F888;

architecture beh of LUT4_F888 is
  signal GND : std_logic ;
  signal VCC : std_logic ;
  signal N_9 : std_logic ;
  signal N_11 : std_logic ;
begin
  N_11 <= I1 and I0 after 100 ps;
  GND <= '0';
  VCC <= '1';
  O <= N_11 or N_9 after 100 ps;
  N_9 <= I3 and I2 after 100 ps;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_CACC is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_CACC;

architecture beh of LUT4_CACC is
  signal GND : std_logic ;
  signal VCC : std_logic ;
  signal N_7 : std_logic ;
  signal I2_I : std_logic ;
begin
  GND <= '0';
  VCC <= '1';
  N_7 <= I3 and I2_I after 100 ps;
  O <= I1 after 100 ps when N_7 = '0' else I0 after 100 ps;
  I2_I <= not I2;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT2_7 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  O :  out std_logic);
end LUT2_7;

architecture beh of LUT2_7 is
  signal I1_I_0 : std_logic ;
  signal I0_I_0 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  O <= I1_I_0 or I0_I_0 after 100 ps;
  I1_I_0 <= not I1;
  I0_I_0 <= not I0;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_B000 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_B000;

architecture beh of LUT4_B000 is
  signal N_7 : std_logic ;
  signal I1_I_0 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  N_7 <= I1_I_0 or I0 after 100 ps;
  I1_I_0 <= not I1;
  O <= N_7 and I3 and I2 after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_0060 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_0060;

architecture beh of LUT4_0060 is
  signal GND : std_logic ;
  signal VCC : std_logic ;
  signal N_14 : std_logic ;
  signal I3_I : std_logic ;
begin
  GND <= '0';
  VCC <= '1';
  N_14 <= I1 xor I0 after 100 ps;
  I3_I <= not I3;
  O <= N_14 and I3_I and I2 after 100 ps;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT2_8 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  O :  out std_logic);
end LUT2_8;

architecture beh of LUT2_8 is
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  O <= I1 and I0 after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_6FF6 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_6FF6;

architecture beh of LUT4_6FF6 is
  signal GND : std_logic ;
  signal VCC : std_logic ;
  signal N_21 : std_logic ;
  signal N_23 : std_logic ;
begin
  GND <= '0';
  VCC <= '1';
  N_23 <= I3 xor I2 after 100 ps;
  O <= N_21 or N_23 after 100 ps;
  N_21 <= I1 xor I0 after 100 ps;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT3_CA is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  O :  out std_logic);
end LUT3_CA;

architecture beh of LUT3_CA is
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  O <= I0 after 100 ps when I2 = '0' else I1 after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT2_B is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  O :  out std_logic);
end LUT2_B;

architecture beh of LUT2_B is
  signal I1_I_0 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  O <= I1_I_0 or I0 after 100 ps;
  I1_I_0 <= not I1;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_8A88 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_8A88;

architecture beh of LUT4_8A88 is
  signal N_6 : std_logic ;
  signal N_7 : std_logic ;
  signal I2_I_0 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  N_7 <= I3 and I2_I_0 after 100 ps;
  N_6 <= N_7 or I1 after 100 ps;
  O <= N_6 and I0 after 100 ps;
  I2_I_0 <= not I2;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_ABAA is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_ABAA;

architecture beh of LUT4_ABAA is
  signal N_7 : std_logic ;
  signal I2_I_0 : std_logic ;
  signal I1_I_0 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  O <= N_7 or I0 after 100 ps;
  I2_I_0 <= not I2;
  I1_I_0 <= not I1;
  N_7 <= I3 and I2_I_0 and I1_I_0 after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT2_4 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  O :  out std_logic);
end LUT2_4;

architecture beh of LUT2_4 is
  signal I0_I_0 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  O <= I1 and I0_I_0 after 100 ps;
  I0_I_0 <= not I0;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT2_2 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  O :  out std_logic);
end LUT2_2;

architecture beh of LUT2_2 is
  signal I1_I_0 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  O <= I1_I_0 and I0 after 100 ps;
  I1_I_0 <= not I1;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT2_6 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  O :  out std_logic);
end LUT2_6;

architecture beh of LUT2_6 is
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  GND <= '0';
  VCC <= '1';
  O <= I1 xor I0 after 100 ps;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_1115 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_1115;

architecture beh of LUT4_1115 is
  signal N_9 : std_logic ;
  signal N_10 : std_logic ;
  signal I0_I_0 : std_logic ;
  signal I1_I_0 : std_logic ;
  signal I3_I_0 : std_logic ;
  signal I2_I_0 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  N_10 <= I3_I_0 and I2_I_0 after 100 ps;
  N_9 <= N_10 or I1_I_0 after 100 ps;
  O <= N_9 and I0_I_0 after 100 ps;
  I0_I_0 <= not I0;
  I1_I_0 <= not I1;
  I3_I_0 <= not I3;
  I2_I_0 <= not I2;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;