i2c_synplify.vhd

Xilinx ISE 官方源代码盘第十章

--
-- Written by Synplicity
-- Mon Jul 26 09:53:03 2004
--

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT3_20 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  O :  out std_logic);
end LUT3_20;

architecture beh of LUT3_20 is
  signal I1_I_0 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  I1_I_0 <= not I1;
  O <= I2 and I1_I_0 and I0 after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_0C2E is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_0C2E;

architecture beh of LUT4_0C2E is
  signal N_6 : std_logic ;
  signal I2_I_0 : std_logic ;
  signal I3_I_0 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  N_6 <= I3_I_0 and I0 after 100 ps;
  O <= N_6 after 100 ps when I1 = '0' else I2_I_0 after 100 ps;
  I2_I_0 <= not I2;
  I3_I_0 <= not I3;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_2AAA is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_2AAA;

architecture beh of LUT4_2AAA is
  signal N_8 : std_logic ;
  signal I3_I_0 : std_logic ;
  signal I2_I_0 : std_logic ;
  signal I1_I_0 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  O <= N_8 and I0 after 100 ps;
  I3_I_0 <= not I3;
  I2_I_0 <= not I2;
  I1_I_0 <= not I1;
  N_8 <= I3_I_0 or I2_I_0 or I1_I_0 after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_2A2E is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_2A2E;

architecture beh of LUT4_2A2E is
  signal N_2 : std_logic ;
  signal N_4 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
  signal I2_I_0 : std_logic ;
  signal I3_I_0 : std_logic ;
begin
  N_4 <= I3_I_0 or I0 after 100 ps;
  N_2 <= N_4 and I2_I_0 after 100 ps;
  O <= I0 after 100 ps when I1 = '0' else N_2 after 100 ps;
  GND <= '0';
  VCC <= '1';
  I2_I_0 <= not I2;
  I3_I_0 <= not I3;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT3_01 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  O :  out std_logic);
end LUT3_01;

architecture beh of LUT3_01 is
  signal I2_I_0 : std_logic ;
  signal I1_I_0 : std_logic ;
  signal I0_I_0 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  I2_I_0 <= not I2;
  I1_I_0 <= not I1;
  I0_I_0 <= not I0;
  O <= I2_I_0 and I1_I_0 and I0_I_0 after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_0080 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_0080;

architecture beh of LUT4_0080 is
  signal I3_I_0 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  I3_I_0 <= not I3;
  O <= I3_I_0 and I2 and I1 and I0 after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT3_EA is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  O :  out std_logic);
end LUT3_EA;

architecture beh of LUT3_EA is
  signal N_4 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  N_4 <= I2 and I1 after 100 ps;
  O <= N_4 or I0 after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_8000 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_8000;

architecture beh of LUT4_8000 is
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  O <= I3 and I2 and I1 and I0 after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_0020 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_0020;

architecture beh of LUT4_0020 is
  signal I3_I_0 : std_logic ;
  signal I1_I_0 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  I3_I_0 <= not I3;
  I1_I_0 <= not I1;
  O <= I3_I_0 and I2 and I1_I_0 and I0 after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_0200 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_0200;

architecture beh of LUT4_0200 is
  signal I2_I_0 : std_logic ;
  signal I1_I_0 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  I2_I_0 <= not I2;
  I1_I_0 <= not I1;
  O <= I3 and I2_I_0 and I1_I_0 and I0 after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_0001 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_0001;

architecture beh of LUT4_0001 is
  signal I3_I_0 : std_logic ;
  signal I2_I_0 : std_logic ;
  signal I1_I_0 : std_logic ;
  signal I0_I_0 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  I3_I_0 <= not I3;
  I2_I_0 <= not I2;
  I1_I_0 <= not I1;
  I0_I_0 <= not I0;
  O <= I3_I_0 and I2_I_0 and I1_I_0 and I0_I_0 after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_0008 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_0008;

architecture beh of LUT4_0008 is
  signal I3_I_0 : std_logic ;
  signal I2_I_0 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  I3_I_0 <= not I3;
  I2_I_0 <= not I2;
  O <= I3_I_0 and I2_I_0 and I1 and I0 after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_B888 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_B888;

architecture beh of LUT4_B888 is
  signal N_4 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  N_4 <= I3 and I2 after 100 ps;
  O <= N_4 after 100 ps when I1 = '0' else I0 after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT3_2A is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  O :  out std_logic);
end LUT3_2A;

architecture beh of LUT3_2A is
  signal N_6 : std_logic ;
  signal I2_I_0 : std_logic ;
  signal I1_I_0 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  N_6 <= I2_I_0 or I1_I_0 after 100 ps;
  O <= N_6 and I0 after 100 ps;
  I2_I_0 <= not I2;
  I1_I_0 <= not I1;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_4044 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_4044;

architecture beh of LUT4_4044 is
  signal N_8 : std_logic ;
  signal I0_I_0 : std_logic ;
  signal I3_I_0 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  N_8 <= I3_I_0 or I2 after 100 ps;
  I0_I_0 <= not I0;
  I3_I_0 <= not I3;
  O <= N_8 and I1 and I0_I_0 after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_1011 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_1011;

architecture beh of LUT4_1011 is
  signal N_9 : std_logic ;
  signal I1_I_0 : std_logic ;
  signal I0_I_0 : std_logic ;
  signal I3_I_0 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  N_9 <= I3_I_0 or I2 after 100 ps;
  I1_I_0 <= not I1;
  I0_I_0 <= not I0;
  I3_I_0 <= not I3;
  O <= N_9 and I1_I_0 and I0_I_0 after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_1101 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_1101;

architecture beh of LUT4_1101 is
  signal N_9 : std_logic ;
  signal I1_I_0 : std_logic ;
  signal I0_I_0 : std_logic ;
  signal I2_I_0 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  N_9 <= I3 or I2_I_0 after 100 ps;
  I1_I_0 <= not I1;
  I0_I_0 <= not I0;
  I2_I_0 <= not I2;
  O <= N_9 and I1_I_0 and I0_I_0 after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_D888 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_D888;

architecture beh of LUT4_D888 is
  signal N_4 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  N_4 <= I3 and I2 after 100 ps;
  O <= N_4 after 100 ps when I0 = '0' else I1 after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_4414 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_4414;

architecture beh of LUT4_4414 is
  signal GND : std_logic ;
  signal VCC : std_logic ;
  signal N_15 : std_logic ;
  signal N_17 : std_logic ;
  signal I0_I : std_logic ;
  signal I3_I : std_logic ;
begin
  N_17 <= I3_I and I2 after 100 ps;
  O <= N_15 and I0_I after 100 ps;
  GND <= '0';
  VCC <= '1';
  N_15 <= N_17 xor I1 after 100 ps;
  I0_I <= not I0;
  I3_I <= not I3;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT3_41 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  O :  out std_logic);
end LUT3_41;

architecture beh of LUT3_41 is
  signal GND : std_logic ;
  signal VCC : std_logic ;
  signal N_13 : std_logic ;
  signal I1_I : std_logic ;
  signal I0_I : std_logic ;
begin
  O <= N_13 and I0_I after 100 ps;
  GND <= '0';
  VCC <= '1';
  N_13 <= I2 xor I1_I after 100 ps;
  I1_I <= not I1;
  I0_I <= not I0;
end beh;