_primary.vhd

Xilinx ISE 官方源代码盘第十章

library verilog;
use verilog.vl_types.all;
entity at24c02 is
    generic(
        device          : string  := "AT24C02";
        device_address  : integer := 80;
        mem_size        : integer := 256;
        page_size       : integer := 8;
        byte_size       : integer := 8;
        addr_size       : integer := 8;
        addr_reg_size   : integer := 8;
        time_out_for_write: integer := 40000;
        taa             : integer := 550;
        send            : integer := 1;
        receive         : integer := 0;
        sending         : string  := "send";
        receiving       : string  := "recv"
    );
    port(
        sda             : inout  vl_logic;
        scl             : in     vl_logic;
        wp              : in     vl_logic
    );
end at24c02;