watch_sc.gfl

Xilinx ISE 官方源代码盘第九章

# Schematic : PDCL (jhdparse)
__projnav/watch_jhdparse_tcl.rsp
# Schematic : PDCL (jhdparse)
__projnav/cnt60_jhdparse_tcl.rsp
# Schematic : PDCL (jhdparse)
__projnav/outs3_jhdparse_tcl.rsp
# Schematic : PDCL (jhdparse)
__projnav/stopwatch_jhdparse_tcl.rsp
# Schematic : PDCL (jhdparse)
__projnav/AndNor2_jhdparse_tcl.rsp
# Schematic : PDCL (jhdparse)
__projnav/stopwatch_jhdparse_tcl.rsp
# Schematic : PDCL (jhdparse)
__projnav/cnt60_jhdparse_tcl.rsp
# XAW : PDCL (jhdparse)
__projnav/DCM1_jhdparse_tcl.rsp
# XAW : Create Schematic Symbol
DCM1.spl
# VHDL : Create Schematic Symbol
__projnav/tb.rsp
decode.spl
__projnav/vhd2spl.err
# VHDL : Create Schematic Symbol
__projnav/tb.rsp
hex2led.spl
__projnav/vhd2spl.err
# Schematic : PDCL (jhdparse)
__projnav/outs3_jhdparse_tcl.rsp
# VHDL : Create Schematic Symbol
__projnav/tb.rsp
stmach_v.spl
__projnav/vhd2spl.err
Coregen : # Regenerate Core
coregen.prj
__projnav/createCoregen.rsp
__projnav/xcoTO_regenCore_tenths.rsp
Coregen : # Regenerate Core
coregen.prj
__projnav/createCoregen.rsp
__projnav/xcoTO_regenCore_tenths.rsp
Coregen : # Regenerate Core
coregen.prj
__projnav/createCoregen.rsp
__projnav/xcoTO_regenCore_tenths.rsp
# Schematic : PDCL (jhdparse)
__projnav/stopwatch_jhdparse_tcl.rsp
# Schematic : PDCL (jhdparse)
__projnav/stopwatch_jhdparse_tcl.rsp
# Schematic : View Verilog Functional Model
stopwatch.vf
# Schematic : View Verilog Functional Model
cnt60.vf
# XAW : View HDL Source (Verilog)
DCM1.v
# Schematic : View Verilog Functional Model
outs3.vf
# XST (Creating Lso File) : 
stopwatch.lso
# xst flow : RunXST
stopwatch.syr
stopwatch.prj
stopwatch.sprj
stopwatch.ana
stopwatch.stx
stopwatch.cmd_log
# Verilog : View Verilog Instantiation Template
DCM1.tfi
__projnav/v2tfi.err
# XST (Creating Lso File) : 
stopwatch.lso
# xst flow : RunXST
stopwatch.syr
stopwatch.prj
stopwatch.sprj
stopwatch.ana
stopwatch.stx
stopwatch.cmd_log
# XAW : PDCL (jhdparse)
__projnav/DCM1_jhdparse_tcl.rsp
# XAW : View HDL Source (Verilog)
DCM1.v
# XST (Creating Lso File) : 
stopwatch.lso
# xst flow : RunXST
stopwatch.syr
stopwatch.prj
stopwatch.sprj
stopwatch.ana
stopwatch.stx
stopwatch.cmd_log
# XST (Creating Lso File) : 
stopwatch.lso
# xst flow : RunXST
stopwatch.syr
stopwatch.prj
stopwatch.sprj
stopwatch.ana
stopwatch.stx
stopwatch.cmd_log
stopwatch.ngc
stopwatch.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
c:\example-9-1\watch_sc/_ngo
stopwatch.ngd
stopwatch_ngdbuild.nav
stopwatch.bld
.untf
stopwatch.cmd_log
# Implementation : Map
stopwatch_map.ncd
stopwatch.ngm
stopwatch.pcf
stopwatch.nc1
stopwatch.mrp
stopwatch_map.mrp
stopwatch.mdf
__projnav/map.log
stopwatch.cmd_log
MAP_NO_GUIDE_FILE_CPF "stopwatch"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
stopwatch.twr
stopwatch.twx
stopwatch.tsi
stopwatch.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
stopwatch.ncd
stopwatch.par
stopwatch.pad
stopwatch_pad.txt
stopwatch_pad.csv
stopwatch.pad_txt
stopwatch.dly
reportgen.log
stopwatch.xpi
stopwatch.grf
stopwatch.itr
stopwatch_last_par.ncd
__projnav/par.log
stopwatch.placed_ncd_tracker
stopwatch.routed_ncd_tracker
stopwatch.cmd_log
PAR_NO_GUIDE_FILE_CPF "stopwatch"
# Generate Programming File
__projnav/stopwatch_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
stopwatch.ut
# Generate Programming File
stopwatch.bgn
stopwatch.rbt
stopwatch.ll
stopwatch.msk
stopwatch.drc
stopwatch.nky
stopwatch.bit
stopwatch.bin
stopwatch.isc
stopwatch.cmd_log
# Schematic : View Verilog Functional Model
stopwatch.vf
# Schematic : View Verilog Functional Model
cnt60.vf
# XAW : View HDL Source (Verilog)
DCM1.v
# Schematic : View Verilog Functional Model
outs3.vf
# XST (Creating Lso File) : 
stopwatch.lso
# xst flow : RunXST
stopwatch.syr
stopwatch.prj
stopwatch.sprj
stopwatch.ana
stopwatch.stx
stopwatch.cmd_log
stopwatch.ngc
stopwatch.ngr
# Schematic : View Verilog Functional Model
stopwatch.vf
# Schematic : View Verilog Functional Model
cnt60.vf
# XAW : View HDL Source (Verilog)
DCM1.v
# Schematic : View Verilog Functional Model
outs3.vf
# XST (Creating Lso File) : 
stopwatch.lso
# xst flow : RunXST
stopwatch.syr
stopwatch.prj
stopwatch.sprj
stopwatch.ana
stopwatch.stx
stopwatch.cmd_log
stopwatch.ngc
stopwatch.ngr
# Project -> New Source -> Architecture Wizard
# Project -> New Source -> Architecture Wizard
# XST (Creating Lso File) : 
stopwatch.lso
# xst flow : RunXST
stopwatch.syr
stopwatch.prj
stopwatch.sprj
stopwatch.ana
stopwatch.stx
stopwatch.cmd_log
stopwatch.ngc
stopwatch.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
c:\example-9-1\watch_sc/_ngo
stopwatch.ngd
stopwatch_ngdbuild.nav
stopwatch.bld
.untf
stopwatch.cmd_log
# Implementation : Map
stopwatch_map.ncd
stopwatch.ngm
stopwatch.pcf
stopwatch.nc1
stopwatch.mrp
stopwatch_map.mrp
stopwatch.mdf
__projnav/map.log
stopwatch.cmd_log
MAP_NO_GUIDE_FILE_CPF "stopwatch"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
stopwatch.twr
stopwatch.twx
stopwatch.tsi
stopwatch.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
stopwatch.ncd
stopwatch.par
stopwatch.pad
stopwatch_pad.txt
stopwatch_pad.csv
stopwatch.pad_txt
stopwatch.dly
reportgen.log
stopwatch.xpi
stopwatch.grf
stopwatch.itr
stopwatch_last_par.ncd
__projnav/par.log
stopwatch.placed_ncd_tracker
stopwatch.routed_ncd_tracker
stopwatch.cmd_log
PAR_NO_GUIDE_FILE_CPF "stopwatch"
# Generate Programming File
__projnav/stopwatch_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
stopwatch.ut
# Generate Programming File
stopwatch.bgn
stopwatch.rbt
stopwatch.ll
stopwatch.msk
stopwatch.drc
stopwatch.nky
stopwatch.bit
stopwatch.bin
stopwatch.isc
stopwatch.cmd_log
# View RTL Schematic
stopwatch.ngr
# Generate Programming File
__projnav/stopwatch_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
stopwatch.ut
# Generate Programming File
stopwatch.bgn
stopwatch.rbt
stopwatch.ll
stopwatch.msk
stopwatch.drc
stopwatch.nky
stopwatch.bit
stopwatch.bin
stopwatch.isc
stopwatch.cmd_log
# Schematic : View Verilog Functional Model
stopwatch.vf
# Schematic : View Verilog Functional Model
cnt60.vf
# XAW : View HDL Source (Verilog)
DCM1.v
# Schematic : View Verilog Functional Model
outs3.vf
# XST (Creating Lso File) : 
stopwatch.lso
# xst flow : RunXST
stopwatch.syr
stopwatch.prj
stopwatch.sprj
stopwatch.ana
stopwatch.stx
stopwatch.cmd_log
stopwatch.ngc
stopwatch.ngr
# Schematic : View Verilog Functional Model
stopwatch.vf
# Schematic : View Verilog Functional Model
cnt60.vf
# XAW : View HDL Source (Verilog)
DCM1.v
# Schematic : View Verilog Functional Model
outs3.vf
# XST (Creating Lso File) : 
stopwatch.lso
# xst flow : RunXST
stopwatch.syr
stopwatch.prj
stopwatch.sprj
stopwatch.ana
stopwatch.stx
stopwatch.cmd_log
stopwatch.ngc
stopwatch.ngr
# Project -> New Source -> Architecture Wizard
# XAW : PDCL (jhdparse)
__projnav/dcm_1_jhdparse_tcl.rsp
# Schematic : View Verilog Functional Model
stopwatch.vf
# Schematic : View Verilog Functional Model
cnt60.vf
# Schematic : View Verilog Functional Model
outs3.vf
# XST (Creating Lso File) : 
stopwatch.lso
# xst flow : RunXST
stopwatch.syr
stopwatch.prj
stopwatch.sprj
stopwatch.ana
stopwatch.stx
stopwatch.cmd_log
stopwatch.ngc
stopwatch.ngr
# Project -> New Source -> Architecture Wizard
# XAW : PDCL (jhdparse)
__projnav/dcm1_jhdparse_tcl.rsp
# Schematic : View Verilog Functional Model
stopwatch.vf
# Schematic : View Verilog Functional Model
cnt60.vf
# XAW : View HDL Source (Verilog)
dcm1.v
# Schematic : View Verilog Functional Model
outs3.vf
# XST (Creating Lso File) : 
stopwatch.lso
# xst flow : RunXST
stopwatch.syr
stopwatch.prj
stopwatch.sprj
stopwatch.ana
stopwatch.stx
stopwatch.cmd_log
stopwatch.ngc
stopwatch.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
c:\example-9-1\watch_sc/_ngo
stopwatch.ngd
stopwatch_ngdbuild.nav
stopwatch.bld
.untf
stopwatch.cmd_log
# Implementation : Map
stopwatch_map.ncd
stopwatch.ngm
stopwatch.pcf
stopwatch.nc1
stopwatch.mrp
stopwatch_map.mrp
stopwatch.mdf
__projnav/map.log
stopwatch.cmd_log
MAP_NO_GUIDE_FILE_CPF "stopwatch"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
stopwatch.twr
stopwatch.twx
stopwatch.tsi
stopwatch.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
stopwatch.ncd
stopwatch.par
stopwatch.pad
stopwatch_pad.txt
stopwatch_pad.csv
stopwatch.pad_txt
stopwatch.dly
reportgen.log
stopwatch.xpi
stopwatch.grf
stopwatch.itr
stopwatch_last_par.ncd
__projnav/par.log
stopwatch.placed_ncd_tracker
stopwatch.routed_ncd_tracker
stopwatch.cmd_log
PAR_NO_GUIDE_FILE_CPF "stopwatch"
# Generate Programming File
__projnav/stopwatch_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
stopwatch.ut
# Generate Programming File
stopwatch.bgn
stopwatch.rbt
stopwatch.ll
stopwatch.msk
stopwatch.drc
stopwatch.nky
stopwatch.bit
stopwatch.bin
stopwatch.isc
stopwatch.cmd_log
# Schematic : View Verilog Functional Model
stopwatch.vf
# Schematic : View Verilog Functional Model
cnt60.vf
# XAW : View HDL Source (Verilog)
dcm1.v
# Schematic : View Verilog Functional Model
outs3.vf
# XST (Creating Lso File) : 
stopwatch.lso
# xst flow : RunXST
stopwatch.syr
stopwatch.prj
stopwatch.sprj
stopwatch.ana
stopwatch.stx
stopwatch.cmd_log
stopwatch.ngc
stopwatch.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
c:\example-9-1\watch_sc/_ngo
stopwatch.ngd
stopwatch_ngdbuild.nav
stopwatch.bld
.untf
stopwatch.cmd_log
# Implementation : Map
stopwatch_map.ncd
stopwatch.ngm
stopwatch.pcf
stopwatch.nc1
stopwatch.mrp
stopwatch_map.mrp
stopwatch.mdf
__projnav/map.log
stopwatch.cmd_log
MAP_NO_GUIDE_FILE_CPF "stopwatch"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
stopwatch.twr
stopwatch.twx
stopwatch.tsi
stopwatch.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
stopwatch.ncd
stopwatch.par
stopwatch.pad
stopwatch_pad.txt
stopwatch_pad.csv
stopwatch.pad_txt
stopwatch.dly
reportgen.log
stopwatch.xpi
stopwatch.grf
stopwatch.itr
stopwatch_last_par.ncd
__projnav/par.log
stopwatch.placed_ncd_tracker
stopwatch.routed_ncd_tracker
stopwatch.cmd_log
PAR_NO_GUIDE_FILE_CPF "stopwatch"
# Generate Programming File
__projnav/stopwatch_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
stopwatch.ut
# Generate Programming File
stopwatch.bgn
stopwatch.rbt
stopwatch.ll
stopwatch.msk
stopwatch.drc
stopwatch.nky
stopwatch.bit
stopwatch.bin
stopwatch.isc
stopwatch.cmd_log
# Schematic : View Verilog Functional Model
stopwatch.vf
# Schematic : View Verilog Functional Model
cnt60.vf
# XAW : View HDL Source (Verilog)
dcm1.v
# Schematic : View Verilog Functional Model
outs3.vf
# XST (Creating Lso File) : 
stopwatch.lso
# xst flow : RunXST
stopwatch.syr
stopwatch.prj
stopwatch.sprj
stopwatch.ana
stopwatch.stx
stopwatch.cmd_log
stopwatch.ngc
stopwatch.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
c:\workstation\ise第二版2004-05-13\cd\example-9-1\watch_sc_v6/_ngo
stopwatch.ngd
stopwatch_ngdbuild.nav
stopwatch.bld
.untf
stopwatch.cmd_log
# Implementation : Map
stopwatch_map.ncd
stopwatch.ngm
stopwatch.pcf
stopwatch.nc1
stopwatch.mrp
stopwatch_map.mrp
stopwatch.mdf
__projnav/map.log
stopwatch.cmd_log
MAP_NO_GUIDE_FILE_CPF "stopwatch"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
stopwatch.twr
stopwatch.twx
stopwatch.tsi
stopwatch.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
stopwatch.ncd
stopwatch.par
stopwatch.pad
stopwatch_pad.txt
stopwatch_pad.csv
stopwatch.pad_txt
stopwatch.dly
reportgen.log
stopwatch.xpi
stopwatch.grf
stopwatch.itr
stopwatch_last_par.ncd
__projnav/par.log
stopwatch.placed_ncd_tracker
stopwatch.routed_ncd_tracker
stopwatch.cmd_log
PAR_NO_GUIDE_FILE_CPF "stopwatch"
# Generate Programming File
__projnav/stopwatch_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
stopwatch.ut
# Generate Programming File
stopwatch.bgn
stopwatch.rbt
stopwatch.ll
stopwatch.msk
stopwatch.drc
stopwatch.nky
stopwatch.bit
stopwatch.bin
stopwatch.isc
stopwatch.cmd_log