syn_pro_stopwatch.prj

Xilinx ISE 官方源代码盘第九章

#-- Synplicity, Inc.
#-- Version 7.2        
#-- Project file J:\ISE\watch_sc\Synplify_Pro\Syn_Pro_stopwatch.prj
#-- Written on Fri Dec 06 11:24:40 2002


#add_file options
add_file -verilog "tenths.v"
add_file -verilog "dcm1.v"
add_file -verilog "decode.v"
add_file -verilog "hex2led.v"
add_file -verilog "STMACH_V.v"
add_file -verilog "black_box.v"
add_file -verilog "virtex2p.v"
add_file -verilog "cnt60.vf"
add_file -verilog "outs3.vf"
add_file -verilog "stopwatch.vf"
add_file -constraint "Syn_Pro_stopwatch.sdc"


#implementation: "Synplify_syn"
impl -add Synplify_syn

#device options
set_option -technology VIRTEX2
set_option -part XC2V80
set_option -package FG256
set_option -speed_grade -6

#compilation/mapping options
set_option -default_enum_encoding default
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 0
set_option -use_fsm_explorer 0

#map options
set_option -frequency 100.000
set_option -fanout_limit 100
set_option -disable_io_insertion 0
set_option -pipe 0
set_option -update_models_cp 0
set_option -verification_mode 0
set_option -modular 0
set_option -retiming 0

#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "Synplify_syn/stopwatch.edf"

#implementation attributes
set_option -vlog_std v2001
set_option -compiler_compatible ""


#implementation: "Synplify_syn_1"
impl -add Synplify_syn_1

#device options
set_option -technology VIRTEX2
set_option -part XC2V80
set_option -package FG256
set_option -speed_grade -6

#compilation/mapping options
set_option -default_enum_encoding default
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 0
set_option -use_fsm_explorer 1
set_option -top_module "stopwatch"

#map options
set_option -frequency 100.000
set_option -fanout_limit 100
set_option -disable_io_insertion 0
set_option -pipe 1
set_option -update_models_cp 0
set_option -verification_mode 0
set_option -modular 0
set_option -retiming 1

#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "Synplify_syn_1/stopwatch.edf"

#implementation attributes
set_option -vlog_std v2001
set_option -compiler_compatible 0
set_option -num_critical_paths 10
set_option -num_startend_points 10
impl -active "Synplify_syn_1"