stopwatch.tlg

Xilinx ISE 官方源代码盘第九章

Selecting top level module stopwatch
Synthesizing module AND2
@W:"J:\ISE\watch_sc\Synplify_Pro\black_box.v":14:7:14:10|Creating black box for empty module AND2

Synthesizing module AND4
@W:"J:\ISE\watch_sc\Synplify_Pro\black_box.v":28:7:28:10|Creating black box for empty module AND4

Synthesizing module AND3
@W:"J:\ISE\watch_sc\Synplify_Pro\black_box.v":22:7:22:10|Creating black box for empty module AND3

Synthesizing module FDCE
Synthesizing module XOR2
@W:"J:\ISE\watch_sc\Synplify_Pro\black_box.v":4:7:4:10|Creating black box for empty module XOR2

Synthesizing module FTCE_MXILINX_cnt60
Synthesizing module VCC
Synthesizing module CB4CE_MXILINX_cnt60
Synthesizing module AND2B1
@W:"J:\ISE\watch_sc\Synplify_Pro\black_box.v":33:7:33:12|Creating black box for empty module AND2B1

Synthesizing module AND4B2
@W:"J:\ISE\watch_sc\Synplify_Pro\black_box.v":40:7:40:12|Creating black box for empty module AND4B2

Synthesizing module INV
Synthesizing module OR2
@W:"J:\ISE\watch_sc\Synplify_Pro\black_box.v":9:7:9:9|Creating black box for empty module OR2

Synthesizing module CD4CE_MXILINX_cnt60
Synthesizing module cnt60
Synthesizing module DCM
Synthesizing module IBUFG
Synthesizing module BUFG
Synthesizing module dcm1
Synthesizing module decode
Synthesizing module hex2led
Synthesizing module IBUF
Synthesizing module OBUF
Synthesizing module outs3
Synthesizing module stmach_v
@N:"J:\ISE\watch_sc\Synplify_Pro\STMACH_V.v":21:1:21:6|Sharing sequential element CLEAR.
Synthesizing module tenths
Synthesizing module stopwatch