stopwatch.ncf

Xilinx ISE 官方源代码盘第九章

#
# Constraints generated by Synplify Pro 7.2, Build 175R
#

# Period Constraints

#Begin clock constraints
NET "clk" TNM_NET = "clk"; 
TIMESPEC "TS_clk" = PERIOD "clk" 10.000 ns HIGH 50.00%; 
NET "rst_int" TNM_NET = "rst_int"; 
TIMESPEC "TS_rst_int" = PERIOD "rst_int" "TS_clk" * 1.000000 HIGH 50.00%; 
#End clock constraints

# Output Constraints
NET "onesout[0]" TNM = "onesout_0_"; 
NET "onesout[1]" TNM = "onesout_0_"; 
NET "onesout[2]" TNM = "onesout_0_"; 
NET "onesout[3]" TNM = "onesout_0_"; 
NET "onesout[4]" TNM = "onesout_0_"; 
NET "onesout[5]" TNM = "onesout_0_"; 
NET "onesout[6]" TNM = "onesout_0_"; 
NET "tensout[0]" TNM = "onesout_0_"; 
NET "tensout[1]" TNM = "onesout_0_"; 
NET "tensout[2]" TNM = "onesout_0_"; 
NET "tensout[3]" TNM = "onesout_0_"; 
NET "tensout[4]" TNM = "onesout_0_"; 
NET "tensout[5]" TNM = "onesout_0_"; 
NET "tensout[6]" TNM = "onesout_0_"; 
TIMESPEC TS_onesout_0__rst_int = FROM "rst_int" TO "onesout_0_" 10.000 ns; 
# Input Constraints
OFFSET = IN : 10.000 : BEFORE clk ;

# Location Constraints

# End of generated constraints