stopwatch.srr

Xilinx ISE 官方源代码盘第九章

$ Start of Compile
#Fri Dec 06 10:14:15 2002

Synplicity Verilog Compiler, version 7.2, Build 112R, built Oct 23 2002
Copyright (C) 1994-2002, Synplicity Inc.  All Rights Reserved

@I::"J:\ISE\watch_sc\Synplify_Pro\tenths.v"
@W:"J:\ISE\watch_sc\Synplify_Pro\tenths.v":31:13:31:18|Unrecognized synthesis directive tools.
@W:"J:\ISE\watch_sc\Synplify_Pro\tenths.v":43:7:43:6|black_box attribute has been renamed to syn_black_box. Change black_box usage to synthesis syn_black_box for upward compatibility.
@W:"J:\ISE\watch_sc\Synplify_Pro\tenths.v":108:12:108:20|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\tenths.v":109:13:109:21|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\tenths.v":113:13:113:21|Unrecognized synthesis directive attribute
@I::"J:\ISE\watch_sc\Synplify_Pro\dcm1.v"
@W:"J:\ISE\watch_sc\Synplify_Pro\dcm1.v":39:13:39:21|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\dcm1.v":40:13:40:21|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\dcm1.v":41:13:41:21|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\dcm1.v":42:13:42:21|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\dcm1.v":43:13:43:21|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\dcm1.v":44:13:44:21|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\dcm1.v":45:13:45:21|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\dcm1.v":46:13:46:21|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\dcm1.v":47:13:47:21|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\dcm1.v":48:13:48:21|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\dcm1.v":49:13:49:21|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\dcm1.v":50:13:50:21|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\dcm1.v":51:13:51:21|Unrecognized synthesis directive attribute
@I::"J:\ISE\watch_sc\Synplify_Pro\decode.v"
@I::"J:\ISE\watch_sc\Synplify_Pro\hex2led.v"
@I::"J:\ISE\watch_sc\Synplify_Pro\STMACH_V.v"
@I::"J:\ISE\watch_sc\Synplify_Pro\black_box.v"
@I::"J:\ISE\watch_sc\Synplify_Pro\virtex2p.v"
@I::"J:\ISE\watch_sc\Synplify_Pro\cnt60.vf"
@W:"J:\ISE\watch_sc\Synplify_Pro\cnt60.vf":17:16:17:24|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\cnt60.vf":18:16:18:24|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\cnt60.vf":51:16:51:24|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\cnt60.vf":53:16:53:24|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\cnt60.vf":55:16:55:24|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\cnt60.vf":57:16:57:24|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\cnt60.vf":95:16:95:24|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\cnt60.vf":100:16:100:24|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\cnt60.vf":105:16:105:24|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\cnt60.vf":110:16:110:24|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\cnt60.vf":148:16:148:24|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\cnt60.vf":151:16:151:24|Unrecognized synthesis directive attribute
@I::"J:\ISE\watch_sc\Synplify_Pro\outs3.vf"
@W:"J:\ISE\watch_sc\Synplify_Pro\outs3.vf":33:16:33:24|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\outs3.vf":34:16:34:24|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\outs3.vf":35:16:35:24|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\outs3.vf":37:16:37:24|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\outs3.vf":38:16:38:24|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\outs3.vf":39:16:39:24|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\outs3.vf":41:16:41:24|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\outs3.vf":42:16:42:24|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\outs3.vf":43:16:43:24|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\outs3.vf":45:16:45:24|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\outs3.vf":46:16:46:24|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\outs3.vf":47:16:47:24|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\outs3.vf":49:16:49:24|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\outs3.vf":50:16:50:24|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\outs3.vf":51:16:51:24|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\outs3.vf":53:16:53:24|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\outs3.vf":54:16:54:24|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\outs3.vf":55:16:55:24|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\outs3.vf":57:16:57:24|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\outs3.vf":58:16:58:24|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\outs3.vf":59:16:59:24|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\outs3.vf":61:16:61:24|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\outs3.vf":62:16:62:24|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\outs3.vf":63:16:63:24|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\outs3.vf":65:16:65:24|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\outs3.vf":66:16:66:24|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\outs3.vf":67:16:67:24|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\outs3.vf":69:16:69:24|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\outs3.vf":70:16:70:24|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\outs3.vf":71:16:71:24|Unrecognized synthesis directive attribute
@I::"J:\ISE\watch_sc\Synplify_Pro\stopwatch.vf"
@W:"J:\ISE\watch_sc\Synplify_Pro\stopwatch.vf":36:16:36:24|Unrecognized synthesis directive attribute
@W:"J:\ISE\watch_sc\Synplify_Pro\stopwatch.vf":38:16:38:24|Unrecognized synthesis directive attribute
Verilog syntax check successful!
Options changed - recompiling
Selecting top level module stopwatch
Synthesizing module AND2
@W:"J:\ISE\watch_sc\Synplify_Pro\black_box.v":14:7:14:10|Creating black box for empty module AND2

Synthesizing module AND4
@W:"J:\ISE\watch_sc\Synplify_Pro\black_box.v":28:7:28:10|Creating black box for empty module AND4

Synthesizing module AND3
@W:"J:\ISE\watch_sc\Synplify_Pro\black_box.v":22:7:22:10|Creating black box for empty module AND3

Synthesizing module FDCE
Synthesizing module XOR2
@W:"J:\ISE\watch_sc\Synplify_Pro\black_box.v":4:7:4:10|Creating black box for empty module XOR2

Synthesizing module FTCE_MXILINX_cnt60
Synthesizing module VCC
Synthesizing module CB4CE_MXILINX_cnt60
Synthesizing module AND2B1
@W:"J:\ISE\watch_sc\Synplify_Pro\black_box.v":33:7:33:12|Creating black box for empty module AND2B1

Synthesizing module AND4B2
@W:"J:\ISE\watch_sc\Synplify_Pro\black_box.v":40:7:40:12|Creating black box for empty module AND4B2

Synthesizing module INV
Synthesizing module OR2
@W:"J:\ISE\watch_sc\Synplify_Pro\black_box.v":9:7:9:9|Creating black box for empty module OR2

Synthesizing module CD4CE_MXILINX_cnt60
Synthesizing module cnt60
Synthesizing module DCM
Synthesizing module IBUFG
Synthesizing module BUFG
Synthesizing module dcm1
Synthesizing module decode
Synthesizing module hex2led
Synthesizing module IBUF
Synthesizing module OBUF
Synthesizing module outs3
Synthesizing module stmach_v
@N:"J:\ISE\watch_sc\Synplify_Pro\STMACH_V.v":21:1:21:6|Sharing sequential element CLEAR.
Synthesizing module tenths
Synthesizing module stopwatch
@END
Process took 0.21 seconds realtime, 0.22 seconds cputime
Synplicity Xilinx Technology Mapper, version 7.2, Build 175R, built Oct 24 2002
Copyright (C) 1994-2002, Synplicity Inc.  All Rights Reserved
Reading constraint file: J:\ISE\watch_sc\Synplify_Pro\Syn_Pro_stopwatch.sdc
Adding property syn_input_delay, value "0.0" to view:work.stopwatch(verilog)
Adding property syn_input_delay_route, value 2 to view:work.stopwatch(verilog)
Adding property syn_output_delay, value "0.0" to view:work.stopwatch(verilog)
Adding property syn_output_delay_route, value 2 to view:work.stopwatch(verilog)
Adding property syn_reg_input_delay_route, value 5, to instance XLXI_5.clkout
Adding property syn_reg_input_delay_route, value 5, to port XLXI_5.clkout



Running FSM Explorer ...

Did not find any FSM for encoding selection. Exiting ...

FSM Explorer successful!
Process took 0.44 seconds realtime, 0.44 seconds cputime
Synplicity Xilinx Technology Mapper, version 7.2, Build 175R, built Oct 24 2002
Copyright (C) 1994-2002, Synplicity Inc.  All Rights Reserved
Reading constraint file: J:\ISE\watch_sc\Synplify_Pro\Syn_Pro_stopwatch.sdc
Adding property syn_input_delay, value "0.0" to view:work.stopwatch(verilog)
Adding property syn_input_delay_route, value 2 to view:work.stopwatch(verilog)
Adding property syn_output_delay, value "0.0" to view:work.stopwatch(verilog)
Adding property syn_output_delay_route, value 2 to view:work.stopwatch(verilog)
Adding property syn_reg_input_delay_route, value 5, to instance XLXI_5.clkout
Adding property syn_reg_input_delay_route, value 5, to port XLXI_5.clkout


Automatic dissolve at startup in view:work.CB4CE_MXILINX_cnt60(verilog) of I_Q3(FTCE_MXILINX_cnt60)
Automatic dissolve at startup in view:work.CB4CE_MXILINX_cnt60(verilog) of I_Q2(FTCE_MXILINX_cnt60)
Automatic dissolve at startup in view:work.CB4CE_MXILINX_cnt60(verilog) of I_Q1(FTCE_MXILINX_cnt60)
Automatic dissolve at startup in view:work.CB4CE_MXILINX_cnt60(verilog) of I_Q0(FTCE_MXILINX_cnt60_I_Q0)
Automatic dissolve at startup in view:work.cnt60(verilog) of I6(CD4CE_MXILINX_cnt60)
Automatic dissolve at startup in view:work.cnt60(verilog) of I5(CB4CE_MXILINX_cnt60)
Automatic dissolve at startup in view:work.stopwatch(verilog) of XLXI_11(outs3)
Automatic dissolve at startup in view:work.stopwatch(verilog) of XLXI_16(dcm1)
Automatic dissolve at startup in view:work.stopwatch(verilog) of XLXI_12(cnt60)
Found 1 global buffers instantiated by user
Net buffering Report for view:work.stopwatch(verilog):
No nets needed buffering.

@N|Retiming summary : 0 registers retimed to 0 

		#####  BEGIN RETIMING REPORT  #####

Retiming summary : 0 registers retimed to 0

Original registers replaced by retiming :
		None

New registers created by retiming :
		None


		#####   END RETIMING REPORT  #####

@N|The option to pack flops in the IOB has not been specified 
@W|Cannot apply constraint syn_reg_input_delay_route to XLXI_5.clkout
Writing Analyst data base J:\ISE\watch_sc\Synplify_Pro\Synplify_syn_1\stopwatch.srm
Writing EDIF Netlist and constraint files
@W:"j:\ise\watch_sc\synplify_pro\stopwatch.vf":43:7:43:12|Blackbox <tenths> is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W:"j:\ise\watch_sc\synplify_pro\cnt60.vf":93:7:93:14|Blackbox <AND4B2> is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
Found clock stopwatch|clk with period 10.00ns 
Found clock stopwatch|rst_int_inferred_clock with period 10.00ns 
Found clock stopwatch|XLXI_16.CLK0_BUF_derived_clock with period 10.00ns 
A default input delay of 0.00ns w.r.t. clock clk:r has been applied to all input ports
A default output delay of 0.00ns w.r.t. clock clk:r has been applied to all output ports


##### START TIMING REPORT #####
# Timing Report written on Fri Dec 06 10:14:18 2002
#


Top view:              stopwatch
Paths requested:       10
Constraint File(s):    J:\ISE\watch_sc\Synplify_Pro\Syn_Pro_stopwatch.sdc
                       
@N| This timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N| Clock constraints cover all FF-to-FF, FF-to-output, input-to-FF and input-to-output paths associated with a particular clock.



Performance Summary 
*******************


Worst slack in design: 0.884

                                             Requested     Estimated     Requested     Estimated               Clock   
Starting Clock                               Frequency     Frequency     Period        Period        Slack     Type    
-----------------------------------------------------------------------------------------------------------------------
clk                                          100.0 MHz     131.7 MHz     10.000        7.594         2.406     declared
stopwatch|XLXI_16.CLK0_BUF_derived_clock     100.0 MHz     138.7 MHz     10.000        7.210         2.790     derived 
stopwatch|rst_int_inferred_clock             100.0 MHz     109.7 MHz     10.000        9.116         0.884     inferred