stopwatch.edf

Xilinx ISE 官方源代码盘第九章

(edif stopwatch
  (edifVersion 2 0 0)
  (edifLevel 0)
  (keywordMap (keywordLevel 0))
  (status
    (written
      (timeStamp 2002 12 6 10 14 18)
      (author "Synplicity, Inc.")
      (program "Synplify" (version "7.2, Build 175R"))
     )
   )
  (library VIRTEX
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           (port CLKFB (direction INPUT))
           (port CLKIN (direction INPUT))
           (port DSSEN (direction INPUT))
           (port PSCLK (direction INPUT))
           (port PSEN (direction INPUT))
           (port PSINCDEC (direction INPUT))
           (port RST (direction INPUT))
           (port CLK0 (direction OUTPUT))
           (port CLK90 (direction OUTPUT))
           (port CLK180 (direction OUTPUT))
           (port CLK270 (direction OUTPUT))
           (port CLK2X (direction OUTPUT))
           (port CLK2X180 (direction OUTPUT))
           (port CLKDV (direction OUTPUT))
           (port CLKFX (direction OUTPUT))
           (port CLKFX180 (direction OUTPUT))
           (port LOCKED (direction OUTPUT))
           (port PSDONE (direction OUTPUT))
         )
       )
    )
    (cell IBUFG (cellType GENERIC)
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         (interface
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       )
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 )
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       (view PRIM (viewType NETLIST)
         (interface
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         )
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       (view PRIM (viewType NETLIST)
         (interface
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         )
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  (library work
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           (port T3 (direction INPUT))
         )
         (contents
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          )
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          )
          (net (rename ones_3 "ones[3]") (joined
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          ))
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         )
       )
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         )
         (contents
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          )
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          )
          (net (rename ones_2 "ones[2]") (joined
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          ))
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          ))
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         )
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       (view netlist (viewType NETLIST)
         (interface