top.v

Xilinx ISE 官方源代码盘第八章

module top (ipad_dll_clk_in, dll_rst, top2a_c, top2b, obuft_out, 
			mod_c_out, moda_data, moda_clk_pad, moda_out, modb_data, 
			modb_clk_pad, modb_out, modc_data, modc_clk_pad, modc_out) ; 
  input ipad_dll_clk_in; 
  input dll_rst; 
  input top2a_c; 
  input top2b; 
  output obuft_out; 
  output mod_c_out; 
  input moda_data; 
  input moda_clk_pad; 
  output moda_out; 
  input modb_data; 
  input modb_clk_pad; 
  output modb_out; 
  input modc_data; 
  input modc_clk_pad; 
  output modc_out; 
//wire ipad_dll_clk_out; 
  wire clk_top; 
  wire dll_clk_out; 
  wire a2top_obuft_i; 
  wire a2c; 
  wire a2b; 
  wire b2top_obuft_t; 
  wire b2c; 
  wire b2a; 
  wire c2and2; 
  wire c2a; 
  wire a_and_c; 
  wire moda_clk; 
  wire modb_clk; 
  wire modc_clk; 
IBUFG ibuf_dll (.I(ipad_dll_clk_in), 
    			.O(dll_clk_in)); 
CLKDLL dll_1 (.CLKIN(dll_clk_in), 
    		  .CLKFB(clk_top), 
    		  .CLK0(dll_clk_out), 
    		  .RST(dll_rst)); 
BUFG globalclk (.O(clk_top), 
    			.I(dll_clk_out)); 
BUFGP bufg_moda (.O(moda_clk), 
    			 .I(moda_clk_pad)); 
BUFGP bufg_modb (.O(modb_clk), 
    			 .I(modb_clk_pad)); 
BUFGP bufg_modc (.O(modc_clk), 
    			  .I(modc_clk_pad)); 
// A simple piece of external logic at top level 
assign a_and_c = c2and2 && b2a; 
// Tri-state output 
assign obuft_out = (!b2top_obuft_t) ? a2top_obuft_i : 1'bz; 

module_a instance_a (.CLK_TOP(clk_top), 
    				 .B2A_IN(b2a), 
     				 .TOP2A_IN(top2a_c), 
    				 .C2A_IN(c2a), 
    				 .MODA_DATA(moda_data), 
    				 .MODA_CLK (moda_clk), 
    			 	 .MODA_OUT (moda_out), 
    				 .A2B_OUT(a2b), 
    				 .A2TOP_OBUFT_I_OUT(a2top_obuft_i), 
    				 .A2C_OUT(a2c)) ; 
module_b instance_b (.CLK_TOP(clk_top), 
    				 .TOP2B_IN(top2b), 
    				 .A2B_IN(a2b), 
    				 .A_AND_C_IN(a_and_c), 
    				 .MODB_DATA(modb_data), 
    				 .MODB_CLK(modb_clk), 
    				 .MODB_OUT(modb_out), 
    				 .B2TOP_OBUFT_T_OUT(b2top_obuft_t), 
    				 .B2C_OUT(b2c), 
    				 .B2A_OUT(b2a)); 
module_c instance_c (.CLK_TOP(clk_top), 
    				 .TOP2A_C_IN(top2a_c), 
    				 .B2C_IN(b2c), 
    				 .A2C_IN(a2c), 
    				 .MODC_DATA(modc_data), 
    				 .MODC_CLK(modc_clk), 
    				 .MODC_OUT(modc_out), 
    				 .C2TOP_OUT(mod_c_out), 
    				 .C2AND2_OUT(c2and2), 
    				 .C2A_OUT(c2a)); 
endmodule 

// Declare modules at top-level to get port directionality 
module module_a ( CLK_TOP, B2A_IN, TOP2A_IN, C2A_IN, MODA_DATA, 
					MODA_CLK, MODA_OUT, A2B_OUT, A2TOP_OBUFT_I_OUT, A2C_OUT) ; 
  input CLK_TOP ; 
  input B2A_IN ; 
  input TOP2A_IN ; 
  input C2A_IN ; 
  input MODA_DATA; 
  input MODA_CLK; 
  output MODA_OUT; 
  output A2B_OUT ; 
  output A2TOP_OBUFT_I_OUT ; 
  output A2C_OUT ; 
endmodule 

module module_b ( CLK_TOP, A2B_IN, TOP2B_IN, A_AND_C_IN, MODB_DATA, 
					MODB_CLK, MODB_OUT, B2A_OUT, B2TOP_OBUFT_T_OUT, B2C_OUT) ; 
  input CLK_TOP ; 
  input A2B_IN ; 
  input TOP2B_IN ; 
  input A_AND_C_IN ; 
  input MODB_DATA; 
  input MODB_CLK; 
  output MODB_OUT; 
  output B2A_OUT ; 
  output B2TOP_OBUFT_T_OUT ; 
  output B2C_OUT ; 
endmodule 

module module_c ( CLK_TOP, B2C_IN, TOP2A_C_IN, A2C_IN, MODC_DATA, 
					MODC_CLK, MODC_OUT, C2A_OUT, C2TOP_OUT, C2AND2_OUT) ; 
  input CLK_TOP ; 
  input B2C_IN ; 
  input TOP2A_C_IN ; 
  input A2C_IN ; 
  input MODC_DATA; 
  input MODC_CLK; 
  output MODC_OUT; 
  output C2A_OUT ; 
  output C2TOP_OUT ; 
  output C2AND2_OUT ; 
endmodule