top.tlg

Xilinx ISE 官方源代码盘第八章

Selecting top level module top
Synthesizing module IBUFG
Synthesizing module CLKDLL
Synthesizing module BUFG
Synthesizing module BUFGP
Synthesizing module module_a
@W:"J:\Example-8-1\Modular_Design\syn_top\top.v":86:7:86:14|Creating black box for empty module module_a

Synthesizing module module_b
@W:"J:\Example-8-1\Modular_Design\syn_top\top.v":100:7:100:14|Creating black box for empty module module_b

Synthesizing module module_c
@W:"J:\Example-8-1\Modular_Design\syn_top\top.v":114:7:114:14|Creating black box for empty module module_c

Synthesizing module top