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Xilinx ISE 官方源代码盘第八章

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<da_list><da><ds><vendor>UNKNOWN</vendor></ds><le leid="1"><type>inst</type><name>instance_c</name></le><msg type="WARNING"><num>600</num><ltext>logical block </ltext><ltext lref="1">'instance_c'</ltext><ltext> with type 'module_c' is unexpanded and will be presumed to be a module</ltext></msg></da><da><ds><vendor>UNKNOWN</vendor></ds><le leid="2"><type>inst</type><name>instance_a</name></le><msg type="WARNING"><num>600</num><ltext>logical block </ltext><ltext lref="2">'instance_a'</ltext><ltext> with type 'module_a' is unexpanded and will be presumed to be a module</ltext></msg></da><da><ds><vendor>UNKNOWN</vendor></ds><le leid="3"><type>net</type><name>top/modc_clk</name></le><msg type="WARNING"><num>478</num><ltext>clock net </ltext><ltext lref="3">'modc_clk'</ltext><ltext> drives no clock pins</ltext></msg></da><da><ds><vendor>UNKNOWN</vendor></ds><le leid="4"><type>net</type><name>top/moda_clk</name></le><msg type="WARNING"><num>478</num><ltext>clock net </ltext><ltext lref="4">'moda_clk'</ltext><ltext> drives no clock pins</ltext></msg></da></da_list>