top.bld

Xilinx ISE 官方源代码盘第八章

Release 5.2i - ngdbuild F.28
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Command Line: ngdbuild -uc module_b.ucf -modular module -active module_b
\example-8-1\modular_design\imp_top\top.ngo 

Launcher: Executing edif2ngd "\example-8-1\modular_design\imp_top\top.edf"
"top.ngo"
INFO:NgdBuild - Release 5.2i - edif2ngd F.28
INFO:NgdBuild - Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.
Writing the design to "top.ngo"...
Reading NGO file "J:/Example-8-1/Modular_Design/Imp_modules/module_b/top.ngo"
...
Reading component libraries for design expansion...
Loading design module "./module_b.ngc"...
INFO:NgdBuild:784 - input buffer 'top2b_ibuf' driving design level port 'top2b'
   is being pushed into module 'instance_b' to enable I/O register usage.
INFO:NgdBuild:784 - input buffer 'modb_data_ibuf' driving design level port
   'modb_data' is being pushed into module 'instance_b' to enable I/O register
   usage.
INFO:NgdBuild:782 - output buffer 'modb_out_obuf' driving design level port
   'modb_out' is being pushed into module 'instance_b' to enable I/O register
   usage.

Annotating constraints to design from file "module_b.ucf" ...

Checking timing specifications ...
INFO:XdmHelpers:862 - TNM "ipad_dll_clk_in", used in period specification
   "TS_ipad_dll_clk_in", was traced through DCM instance "dll_1" to the loads on
   the CLK0 output.
Checking expanded design ...
WARNING:NgdBuild:600 - logical block 'instance_c' with type 'module_c' is
   unexpanded and will be presumed to be a module.
WARNING:NgdBuild:600 - logical block 'instance_a' with type 'module_a' is
   unexpanded and will be presumed to be a module.
WARNING:NgdBuild:478 - clock net 'modc_clk' drives no clock pins
WARNING:NgdBuild:478 - clock net 'moda_clk' drives no clock pins

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   4

Writing NGD file "top.ngd" ...

Writing NGDBUILD log file "top.bld"...