📄 top.srr
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$ Start of Compile
#Wed Jun 02 03:08:09 2004
Synplicity Verilog Compiler, version Compilers 2.6.0, Build 102R, built Jan 27 2004
Copyright (C) 1994-2004, Synplicity Inc. All Rights Reserved
@I::"D:\CD\EXAMPLE-8-2\synplify_syn\module_b.v"
@I::"D:\CD\EXAMPLE-8-2\synplify_syn\module_c.v"
@I::"D:\CD\EXAMPLE-8-2\synplify_syn\module_a.v"
@I::"D:\CD\EXAMPLE-8-2\synplify_syn\virtex2.v"
@I::"D:\CD\EXAMPLE-8-2\synplify_syn\top.v"
Verilog syntax check successful!
File D:\CD\EXAMPLE-8-2\synplify_syn\module_b.v changed - recompiling
Selecting top level module top
Synthesizing module IBUFG
Synthesizing module CLKDLL
Synthesizing module BUFG
Synthesizing module BUFGP
Synthesizing module module_a
Synthesizing module module_b
Synthesizing module module_c
Synthesizing module top
@END
Process took 0h:0m:0s realtime, 0h:0m:0s cputime
###########################################################[
Synplicity Xilinx Technology Mapper, version 7.3.5, Build 256R, built Mar 25 2004
Copyright (C) 1994-2004, Synplicity Inc. All Rights Reserved
Reading constraint file: D:\CD\EXAMPLE-8-2\synplify_syn\Syn_Incremental.sdc
@N: MF104 :"d:\cd\example-8-2\synplify_syn\module_a.v":1:7:1:14|Found Compile Point of type locked on View view:work.module_a(verilog)
@N: MF104 :"d:\cd\example-8-2\synplify_syn\module_b.v":1:7:1:14|Found Compile Point of type locked on View view:work.module_b(verilog)
@N: MF104 :"d:\cd\example-8-2\synplify_syn\module_c.v":1:7:1:14|Found Compile Point of type locked on View view:work.module_c(verilog)
@N: MF105 |Performing bottom up mapping of Compile point view:work.module_a(verilog)
@N: MF107 :"d:\cd\example-8-2\synplify_syn\module_a.v":1:7:1:14|Old Database upto date, No need to remap Compile point view:work.module_a(verilog)
@N: MF105 |Performing bottom up mapping of Compile point view:work.module_b(verilog)
@N: MF106 :"d:\cd\example-8-2\synplify_syn\module_b.v":1:7:1:14|Mapping Compile point view:work.module_b(verilog) because
RTL and/or Constraints changed.
@W: MF112 :"d:\cd\example-8-2\synplify_syn\module_b.v":1:7:1:14|Please supply a constraint file for compile point module_b
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
------------------------------------------------------------
Net buffering Report for view:work.module_b(verilog):
No nets needed buffering.
@N: MF105 |Performing bottom up mapping of Compile point view:work.module_c(verilog)
@N: MF107 :"d:\cd\example-8-2\synplify_syn\module_c.v":1:7:1:14|Old Database upto date, No need to remap Compile point view:work.module_c(verilog)
@N: MF105 |Performing bottom up mapping of Top level view:work.top(verilog)
@N: MF107 :"d:\cd\example-8-2\synplify_syn\top.v":1:7:1:9|Old Database upto date, No need to remap Top level view:work.top(verilog)
Summary of Compile Points
Name Status Reason
-----------------------------------------
module_a Unchanged -
module_b Remapped Design changed
module_c Unchanged -
top Unchanged -
=========================================
Writing Analyst data base D:\CD\EXAMPLE-8-2\synplify_syn\rev_1\top.srm
Writing EDIF Netlist and constraint files
Found clock top|ipad_dll_clk_in with period 1000.00ns
Found clock top|moda_clk_pad with period 1000.00ns
Found clock top|modb_clk_pad with period 1000.00ns
Found clock top|modc_clk_pad with period 1000.00ns
Found clock top|dll_clk_out_derived_clock with period 1000.00ns
##### START OF TIMING REPORT #####[
# Timing Report written on Wed Jun 02 03:08:13 2004
#
Top view: top
Requested Frequency: 1.0 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s): D:\CD\EXAMPLE-8-2\synplify_syn\Syn_Incremental.sdc
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..
@N: MT196 |Clock constraints cover all FF-to-FF, FF-to-output, input-to-FF and input-to-output paths associated with a particular clock..
Performance Summary
*******************
Worst slack in design: 995.023
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
----------------------------------------------------------------------------------------------------------------------------------------------------------------
top|dll_clk_out_derived_clock 1.0 MHz 200.9 MHz 1000.000 4.977 995.023 derived (from top|ipad_dll_clk_in) Inferred_clkgroup_6
top|moda_clk_pad 1.0 MHz 200.9 MHz 1000.000 4.977 995.023 inferred Inferred_clkgroup_7
top|modb_clk_pad 1.0 MHz 209.2 MHz 1000.000 4.779 995.221 inferred Inferred_clkgroup_8
top|modc_clk_pad 1.0 MHz 200.9 MHz 1000.000 4.977 995.023 inferred Inferred_clkgroup_9
================================================================================================================================================================
Clock Relationships
*******************
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
------------------------------------------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
------------------------------------------------------------------------------------------------------------------------------------------------------
top|moda_clk_pad top|moda_clk_pad | 1000.000 995.023 | No paths - | No paths - | No paths -
top|moda_clk_pad top|modc_clk_pad | Diff grp - | No paths - | No paths - | No paths -
top|moda_clk_pad top|dll_clk_out_derived_clock | Diff grp - | No paths - | No paths - | No paths -
top|modb_clk_pad top|modb_clk_pad | 1000.000 995.221 | No paths - | No paths - | No paths -
top|modb_clk_pad top|modc_clk_pad | Diff grp - | No paths - | No paths - | No paths -
top|modb_clk_pad top|dll_clk_out_derived_clock | Diff grp - | No paths - | No paths - | No paths -
top|modc_clk_pad top|moda_clk_pad | Diff grp - | No paths - | No paths - | No paths -
top|modc_clk_pad top|modc_clk_pad | 1000.000 995.023 | No paths - | No paths - | No paths -
top|modc_clk_pad top|dll_clk_out_derived_clock | Diff grp - | No paths - | No paths - | No paths -
top|dll_clk_out_derived_clock top|moda_clk_pad | Diff grp - | No paths - | No paths - | No paths -
top|dll_clk_out_derived_clock top|modb_clk_pad | Diff grp - | No paths - | No paths - | No paths -
top|dll_clk_out_derived_clock top|modc_clk_pad | Diff grp - | No paths - | No paths - | No paths -
top|dll_clk_out_derived_clock top|dll_clk_out_derived_clock | 1000.000 995.023 | No paths - | No paths - | No paths -
======================================================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
Interface Information
*********************
Input Ports:
Port Starting User Arrival Required
Name Reference Constraint Time Time Slack
Clock
--------------------------------------------------------------------------------------------------------------
dll_rst NA NA NA NA NA
ipad_dll_clk_in NA NA NA NA NA
moda_clk_pad NA NA NA NA NA
moda_data top|dll_clk_out_derived_clock (rising) 0.000 0.000 998.648 998.648
modb_clk_pad NA NA NA NA NA
modb_data top|dll_clk_out_derived_clock (rising) 0.000 0.000 998.648 998.648
modc_clk_pad NA NA NA NA NA
modc_data top|dll_clk_out_derived_clock (rising) 0.000 0.000 998.648 998.648
top2a_c top|dll_clk_out_derived_clock (rising) 0.000 0.000 998.591 998.591
top2b top|dll_clk_out_derived_clock (rising) 0.000 0.000 998.648 998.648
==============================================================================================================
Output Ports:
Port Starting User Arrival Required
Name Reference Constraint Time Time Slack
Clock
--------------------------------------------------------------------------------------------------------
mod_c_out top|modc_clk_pad (rising) NA 4.977 1000.000 995.023
moda_out top|dll_clk_out_derived_clock (rising) NA 4.977 1000.000 995.023
modb_out top|dll_clk_out_derived_clock (rising) NA 4.977 1000.000 995.023
modc_out top|dll_clk_out_derived_clock (rising) NA 4.977 1000.000 995.023
obuft_out top|moda_clk_pad (rising) NA 4.977 1000.000 995.023
========================================================================================================
====================================
Detailed Report for Clock: top|dll_clk_out_derived_clock
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
---------------------------------------------------------------------------------------------------------------
instance_a.MODA_OUT top|dll_clk_out_derived_clock FDS Q MODA_OUT 0.449 995.023
instance_b.MODB_OUT top|dll_clk_out_derived_clock FDR Q MODB_OUT 0.449 995.023
instance_c.MODC_OUT top|dll_clk_out_derived_clock FDS Q MODC_OUT 0.449 995.023
instance_b.Q0_OUT top|dll_clk_out_derived_clock FD Q Q0_OUT 0.449 998.006
instance_c.Q0_OUT top|dll_clk_out_derived_clock FD Q Q0_OUT 0.449 998.006
instance_a.Q0_OUT top|dll_clk_out_derived_clock FD Q Q0_OUT 0.449 998.006
instance_a.Q2_OUT top|dll_clk_out_derived_clock FD Q Q2_OUT 0.449 998.006
instance_c.Q2_OUT top|dll_clk_out_derived_clock FD Q Q2_OUT 0.449 998.006
instance_b.Q2_OUT top|dll_clk_out_derived_clock FD Q Q2_OUT 0.449 998.006
top2a_c top|dll_clk_out_derived_clock Port top2a_c top2a_c 0.000 998.591
===============================================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
----------------------------------------------------------------------------------------------------------------------
moda_out top|dll_clk_out_derived_clock Port moda_out moda_out 1000.000 995.023
modb_out top|dll_clk_out_derived_clock Port modb_out modb_out 1000.000 995.023
modc_out top|dll_clk_out_derived_clock Port modc_out modc_out 1000.000 995.023
instance_a.A2B_OUT top|dll_clk_out_derived_clock FDR D A2B_OUTc 999.707 998.006
instance_b.B2A_OUT top|dll_clk_out_derived_clock FDR D B2A_OUTc 999.707 998.006
instance_c.C2AND2_OUT top|dll_clk_out_derived_clock FDR D C2A_OUTc 999.707 998.006
instance_a.MODA_OUT top|dll_clk_out_derived_clock FDS D A2C_OUTs_i 999.707 998.006
instance_b.MODB_OUT top|dll_clk_out_derived_clock FDR D B2C_OUTc 999.707 998.006
instance_c.MODC_OUT top|dll_clk_out_derived_clock FDS D MODC_OUTs_i 999.707 998.006
instance_c.Q2_OUT top|dll_clk_out_derived_clock FD D TOP2A_C_IN 999.707 998.591
======================================================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 1000.000
= Required time: 1000.000
- Propagation time: 4.977
= Slack (critical) : 995.023
Number of logic level(s): 1
Starting point: instance_a.MODA_OUT / Q
Ending point: moda_out / moda_out
The start point is clocked by top|dll_clk_out_derived_clock [rising] on pin C
The end point is clocked by top|dll_clk_out_derived_clock [rising]
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
--------------------------------------------------------------------------------------
instance_a.MODA_OUT FDS Q Out 0.449 0.449 -
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