top.plg

Xilinx ISE 官方源代码盘第八章

@P:  Worst Slack : 995.023
@P:  top|dll_clk_out_derived_clock - Estimated Frequency : 200.9 MHz
@P:  top|dll_clk_out_derived_clock - Requested Frequency : 1.0 MHz
@P:  top|dll_clk_out_derived_clock - Estimated Period : 4.977
@P:  top|dll_clk_out_derived_clock - Requested Period : 1000.000
@P:  top|dll_clk_out_derived_clock - Slack : 995.023
@P:  top|moda_clk_pad - Estimated Frequency : 200.9 MHz
@P:  top|moda_clk_pad - Requested Frequency : 1.0 MHz
@P:  top|moda_clk_pad - Estimated Period : 4.977
@P:  top|moda_clk_pad - Requested Period : 1000.000
@P:  top|moda_clk_pad - Slack : 995.023
@P:  top|modb_clk_pad - Estimated Frequency : 209.2 MHz
@P:  top|modb_clk_pad - Requested Frequency : 1.0 MHz
@P:  top|modb_clk_pad - Estimated Period : 4.779
@P:  top|modb_clk_pad - Requested Period : 1000.000
@P:  top|modb_clk_pad - Slack : 995.221
@P:  top|modc_clk_pad - Estimated Frequency : 200.9 MHz
@P:  top|modc_clk_pad - Requested Frequency : 1.0 MHz
@P:  top|modc_clk_pad - Estimated Period : 4.977
@P:  top|modc_clk_pad - Requested Period : 1000.000
@P:  top|modc_clk_pad - Slack : 995.023
@P: top Part : xc2v500fg256-6
@P: top I/O primitives : 12
@P: top I/O Register bits : 0
@P: top Register bits (Non I/O) : 24 (0%)
@P: top Total Luts : 7 (0%)