rtl.srd

Xilinx ISE 官方源代码盘第八章

f "noname"; #file 0
f "d:\cd\example-8-2\synplify_syn\module_b.v"; #file 1
f "d:\cd\example-8-2\synplify_syn\module_c.v"; #file 2
f "d:\cd\example-8-2\synplify_syn\module_a.v"; #file 3
f "d:\cd\example-8-2\synplify_syn\virtex2.v"; #file 4
f "d:\cd\example-8-2\synplify_syn\top.v"; #file 5
VNAME 'work.module_c.verilog'; # view id 0
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