top.vhd

Xilinx ISE 官方源代码盘第八章

library IEEE; 
use IEEE.std_logic_1164.all; 
entity top is port (ipad_dll_clk_in: in std_logic; 
    dll_rst : in std_logic; 
    top2a_c: in std_logic; 
    top2b: in std_logic; 
    obuft_out: out std_logic; 
    mod_c_out: out std_logic; 
    moda_clk_pad: in std_logic; 
    moda_data: in std_logic; 
    moda_out: out std_logic; 
    modb_clk_pad: in std_logic; 
    modb_data: in std_logic; 
    modb_out: out std_logic; 
    modc_clk_pad: in std_logic; 
    modc_data: in std_logic; 
    modc_out: out std_logic 
) ; 
end top; 
architecture modular of top is 
signal dll_clk_in : std_logic; 
signal clk_top : std_logic; 
signal dll_clk_out: std_logic; 
signal a2top_obuft_i: std_logic; 
signal a2c: std_logic; 
signal a2b: std_logic; 
signal b2top_obuft_t: std_logic; 
signal b2c: std_logic; 
signal b2a: std_logic; 
signal c2and2: std_logic; 
signal c2a: std_logic; 
signal a_and_c: std_logic; 
signal moda_clk: std_logic; 
signal modb_clk: std_logic; 
signal modc_clk: std_logic; 
component IBUFG is port
( I:in std_logic;
  O:out std_logic); 
end component; 
component CLKDLL is port ( 
  CLKIN : in std_logic; 
  CLKFB : in std_logic; 
  RST : in std_logic; 
  CLK0 : out std_logic; 
  CLK90 : out std_logic; 
  CLK180 : out std_logic; 
  CLK270 : out std_logic; 
  CLKDV : out std_logic; 
  CLK2X : out std_logic; 
  LOCKED : out std_logic); 
  end component;
   
component BUFG is port (
  I:in std_logic; 
  O:out std_logic); 
  end component; 
component BUFGP 
  port ( 
  I : in std_logic; 
  O : out std_logic); 
  end component; 
-- Declare modules at top-level to get port directionality 
component module_a is port( CLK_TOP: in std_logic; 
    B2A_IN: in std_logic; 
    TOP2A_IN: in std_logic; 
    C2A_IN: in std_logic; 
    MODA_DATA : in std_logic; 
    MODA_CLK : in std_logic; 
    A2B_OUT: out std_logic; 
    A2TOP_OBUFT_I_OUT: out std_logic; 
    A2c_ouT: out std_logic; 
    MODA_OUT : out std_logic 
); 
end component; 
component module_b is port( CLK_TOP: in std_logic; 
    A2B_IN: in std_logic; 
    TOP2B_IN: in std_logic; 
    A_AND_C_IN: in std_logic; 
    MODB_DATA: in std_logic; 
    MODB_CLK: in std_logic; 
    MODB_OUT : out std_logic; 
    B2A_OUT: out std_logic; 
    B2TOP_OBUFT_T_OUT: out std_logic; 
    B2C_OUT: out std_logic); 
end component; 
component module_c is port( CLK_TOP: in std_logic; 
    B2C_IN: in std_logic; 
    TOP2A_C_IN: in std_logic; 
    A2C_IN: in std_logic; 
    MODC_DATA: in std_logic; 
    MODC_CLK: in std_logic; 
    MODC_OUT: out std_logic; 
    C2A_OUT: out std_logic; 
    C2TOP_OUT: out std_logic; 
    C2AND2_OUT: out std_logic); 
end component; 
begin 
ibuf_dll: IBUFG port map(I =>ipad_dll_clk_in, 
    			 O => dll_clk_in); 
dll_1: CLKDLL port map (CLKIN => dll_clk_in, 
    			CLKFB => clk_top, 
    			CLK0 => dll_clk_out, 
    			RST => dll_rst); 
globalclk: BUFG port map	(O => clk_top, 
    			 	I => dll_clk_out); 
bufg_moda : BUFGP port map 	(O => moda_clk, 
    				I => moda_clk_pad); 
bufg_modb : BUFGP port map 	(O => modb_clk, 
    				I => modb_clk_pad); 
bufg_modc : BUFGP port map 	( O => modc_clk, 
    				I => modc_clk_pad); 
-- A simple piece of external logic at top level 
a_and_c <= c2and2 and b2a; 
-- Tri-state output 
obuft_out <= a2top_obuft_i when b2top_obuft_t = '0' else 'Z'; 
instance_a: module_a port map (CLK_TOP =>clk_top, 
    TOP2A_IN =>top2a_c, 
    C2A_IN =>c2a, 
    B2A_IN => b2a, 
    MODA_DATA => moda_data, 
    MODA_CLK => moda_clk, 
    MODA_OUT => moda_out, 
    A2B_OUT => a2b, 
    A2TOP_OBUFT_I_OUT => a2top_obuft_i, 
    A2C_OUT => a2c) ; 
instance_b: module_b port map ( CLK_TOP => clk_top, 
    TOP2B_IN => top2b, 
    A2B_IN => a2b, 
    A_AND_C_IN => a_and_c, 
    MODB_DATA => modb_data, 
    MODB_CLK => modb_clk, 
    MODB_OUT => modb_out, 
    B2TOP_OBUFT_T_OUT => b2top_obuft_t, 
    B2C_OUT => b2c, 
    B2A_OUT => b2a); 
instance_c: module_c port map ( CLK_TOP => clk_top, 
    TOP2A_C_IN => top2a_c, 
    B2C_IN => b2c, 
    A2C_IN => a2c, 
    MODC_DATA => modc_data, 
    MODC_CLK => modc_clk, 
    MODC_OUT => modc_out, 
    C2TOP_OUT => mod_c_out, 
    C2AND2_OUT => c2and2, 
    C2A_OUT => c2a); 
end modular;