module_a.vhd

Xilinx ISE 官方源代码盘第八章

library IEEE; 
use IEEE.std_logic_1164.all; 
entity module_a is port ( CLK_TOP : in std_logic; 
    B2A_IN: in std_logic; 
    TOP2A_IN: in std_logic; 
    C2A_IN: in std_logic; 
    MODA_DATA : in std_logic; 
    MODA_CLK : in std_logic; 
    MODA_OUT : out std_logic; 
    A2B_OUT: out std_logic; 
    A2TOP_OBUFT_I_OUT: out std_logic; 
    A2C_OUT: out std_logic) ; 
end module_a; 
architecture modular of module_a is 
-- add your signal declarations here 
signal Q0_OUT, Q1_OUT, Q2_OUT, Q3_OUT : std_logic; 
signal AND4_OUT: std_logic ; 
signal OR4_OUT : std_logic; 
begin 
AND4_OUT <= Q0_OUT and Q1_OUT and Q2_OUT and Q3_OUT ; 
OR4_OUT <= Q0_OUT or Q1_OUT or Q2_OUT or Q3_OUT ; 
TOP_CLK: process(CLK_TOP) 
begin 
if (CLK_TOP 'event and CLK_TOP = '1') then
  Q0_OUT <= MODA_DATA ; 
  Q2_OUT <= TOP2A_IN ; 
  MODA_OUT <= OR4_OUT ; 
  A2B_OUT <= AND4_OUT ; 
end if; 
end process TOP_CLK; 
CLK_MODA: process(MODA_CLK) 
begin 
if (MODA_CLK 'event and MODA_CLK = '1') then 
  Q1_OUT <= B2A_IN ; 
  Q3_OUT <= C2A_IN ; 
  A2TOP_OBUFT_I_OUT <= AND4_OUT ; 
  A2C_OUT <= OR4_OUT ; 
end if; 
end process CLK_MODA; 
end modular;