incremental_demo.gfl

Xilinx ISE 官方源代码盘第八章

# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
d:\cd\example-8-2\incremental_design\incremental_demo/_ngo
top.ngd
top_ngdbuild.nav
top.bld
.untf
top.cmd_log
# Create Area Constraints
__projnav/parentCreateAreaConstraintsApp_tcl.rsp
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
d:\cd\example-8-2\incremental_design\incremental_demo/_ngo
top.ngd
top_ngdbuild.nav
top.bld
top.ucf.untf
top.cmd_log
# Implementation : Map
top_map.ncd
top.ngm
top.pcf
top.nc1
top.mrp
top_map.mrp
top.mdf
__projnav/map.log
top.cmd_log
MAP_NO_GUIDE_FILE_CPF "top"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
top.twr
top.twx
top.tsi
top.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
top.ncd
top.par
top.pad
top_pad.txt
top_pad.csv
top.pad_txt
top.dly
reportgen.log
top.xpi
top.grf
top.itr
top_last_par.ncd
__projnav/par.log
top.placed_ncd_tracker
top.routed_ncd_tracker
top.cmd_log
PAR_NO_GUIDE_FILE_CPF "top"
# Generate Programming File
__projnav/top_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
top.ut
# Generate Programming File
top.bgn
top.rbt
top.ll
top.msk
top.drc
top.nky
top.bit
top.bin
top.isc
top.cmd_log
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
d:\cd\example-8-2\incremental_design\incremental_demo/_ngo
top.ngd
top_ngdbuild.nav
top.bld
top.ucf.untf
top.cmd_log
# Implementation : Map
top_map.ncd
top.ngm
top.pcf
top.nc1
top.mrp
top_map.mrp
top.mdf
__projnav/map.log
top.cmd_log
MAP_NO_GUIDE_FILE_CPF "top"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
top.twr
top.twx
top.tsi
top.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
top.ncd
top.par
top.pad
top_pad.txt
top_pad.csv
top.pad_txt
top.dly
reportgen.log
top.xpi
top.grf
top.itr
top_last_par.ncd
__projnav/par.log
top.placed_ncd_tracker
top.routed_ncd_tracker
top.cmd_log
PAR_NO_GUIDE_FILE_CPF "top"
# Generate Programming File
__projnav/top_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
top.ut
# Generate Programming File
top.bgn
top.rbt
top.ll
top.msk
top.drc
top.nky
top.bit
top.bin
top.isc
top.cmd_log
# Implementation : Manually Place & Route (FPGA Editor)
top_map_fpga_editor.log
top_fpga_editor.out
top_fpga_editor.log
__projnav/mfea_tcl.rsp
# Implmentation : Floorplan Design Post-Map (Floorplanner)
__projnav/mapFloorPlanner.rsp
top_map.mfp
# Create Area Constraints
__projnav/parentCreateAreaConstraintsApp_tcl.rsp