top.par

Xilinx ISE 官方源代码盘第八章

Release 6.2i Par G.30
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

LATTICE-WESTOR::  Wed Jun 02 03:29:11 2004


C:/eda/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 -gf
D:\CD\Example-8-2\Incremental_design\Incremental_demo\top_guide.ncd -gm
incremental top_map.ncd top.ncd top.pcf 


Constraints file: top.pcf

Loading device database for application Par from file "top_map.ncd".
   "top" is an NCD, version 2.38, device xc2v500, package fg256, speed -6
Loading device for application Par from file '2v500.nph' in environment
C:/eda/Xilinx.
The STEPPING level for this design is 1.
Device speed data version:  PRODUCTION 1.118 2004-03-12.


Starting Guide File Processing.

Loading device database for application Par from file
"D:\CD\Example-8-2\Incremental_design\Incremental_demo\top_guide.ncd".
   "top" is an NCD, version 2.38, device xc2v500, package fg256, speed -6
The STEPPING level for this design is 1.

Finished Guide File Processing.

Xilinx Place and Route Guide Results File
=========================================

Guide Summary Report:

Incremental Design Totals:
   Area Groups Guided:   2 out of   3

Guide file:
"D:\CD\Example-8-2\Incremental_design\Incremental_demo\top_guide.ncd"

   Area Group AG_instance_c was guided.
   Area Group AG_instance_b was re-implemented.
   Area Group AG_instance_a was guided.
   Ungrouped Logic was re-implemented.
For a detailed guide report refer to the "top.grf" file.

Device utilization summary:

   Number of External IOBs            15 out of 172     8%
      Number of LOCed External IOBs    7 out of 15     46%

   Number of SLICEs                   15 out of 3072    1%

   Number of BUFGMUXs                  4 out of 16     25%
   Number of DCMs                      1 out of 8      12%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:98970b) REAL time: 2 secs 

Phase 2.2
.
Phase 2.2 (Checksum:1312cfe) REAL time: 2 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 2 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 2 secs 

Phase 5.8
.
Phase 5.8 (Checksum:9960a5) REAL time: 2 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 2 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 2 secs 

Phase 8.24
Phase 8.24 (Checksum:4c4b3f8) REAL time: 2 secs 

Phase 9.27
Phase 9.27 (Checksum:55d4a77) REAL time: 2 secs 

Writing design to file top.ncd.

Total REAL time to Placer completion: 2 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 63 unrouted;       REAL time: 2 secs 

Phase 2: 25 unrouted;       REAL time: 2 secs 

Phase 3: 2 unrouted;       REAL time: 2 secs 

Phase 4: 0 unrouted;       REAL time: 2 secs 

Total REAL time to Router completion: 3 secs 
Total CPU time to Router completion: 2 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+-------------------------+----------+------+------+------------+-------------+
|        Clock Net        | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+-------------------------+----------+------+------+------------+-------------+
|           clk_top       | BUFGMUX4S| No   |   13 |  0.154     |  0.795      |
+-------------------------+----------+------+------+------------+-------------+
|          moda_clk       | BUFGMUX7S| No   |    4 |  0.128     |  0.795      |
+-------------------------+----------+------+------+------------+-------------+
|          modc_clk       | BUFGMUX0P| No   |    4 |  0.153     |  0.797      |
+-------------------------+----------+------+------+------------+-------------+
|          modb_clk       | BUFGMUX3P| No   |    4 |  0.004     |  0.766      |
+-------------------------+----------+------+------+------------+-------------+


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 118


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        0.832
   The MAXIMUM PIN DELAY IS:                               3.184
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   1.724

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
          71          17           2           1           0           0

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 3 secs 
Total CPU time to PAR completion: 2 secs 

Peak Memory Usage:  63 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file top.ncd.


PAR done.