incremental_demo.npl

Xilinx ISE 官方源代码盘第八章

JDF G
// Created by Project Navigator ver 1.0
PROJECT Incremental_demo
DESIGN incremental_demo
DEVFAM virtex2
DEVFAMTIME 0
DEVICE xc2v500
DEVICETIME 0
DEVPKG fg256
DEVPKGTIME 0
DEVSPEED -6
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE EDIF
TOPLEVELMODULETYPETIME 1086112832
DEVSYNTHESISTOOL Synplify Pro (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Modelsim
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL Verilog
GENERATEDSIMULATIONMODELTIME 0
DOCUMENT top.ncf
SOURCE top.edf
DEPASSOC top top.ucf
[Normal]
xilxMapGuideDesign=edif, virtex2, EDIF.t_map, 1086118033, D:\CD\Example-8-2\Incremental_design\Incremental_demo\top_map_guide.ncd
xilxMapGuideMode=edif, virtex2, EDIF.t_map, 1086118033, Incremental
xilxPARguideDesign=edif, virtex2, EDIF.t_par, 1086118145, D:\CD\Example-8-2\Incremental_design\Incremental_demo\top_guide.ncd
xilxPARguideMode=edif, virtex2, EDIF.t_par, 1086118145, Incremental
[STRATEGY-LIST]
Normal=True