watchver.npl

Xilinx ISE 官方源代码盘第七章 Part 2

JDF F
// Created by Project Navigator ver 1.0
PROJECT watchver
DESIGN watchver Normal
DEVFAM virtexe
DEVFAMTIME 1039249802
DEVICE xcv300e
DEVICETIME 1039249802
DEVPKG bg432
DEVPKGTIME 1039249802
DEVSPEED -6
DEVSPEEDTIME 1016218486
FLOW XST Verilog
FLOWTIME 1016218486
STIMULUS stopwatch_tb.tbw Normal
STIMULUS stopwatch_tb_timing.tf Normal
DOCUMENT readme
MODULE decode.v
MODSTYLE decode Normal
MODULE statmach.v
MODSTYLE statmach Normal
MODULE smallcntr.v
MODSTYLE smallcntr Normal
MODULE cnt60.v
MODSTYLE cnt60 Normal
MODULE stopwatch.v
MODSTYLE stopwatch Normal
MODULE hex2led.v
MODSTYLE hex2led Normal
MODULE tenths.xco
MODSTYLE tenths Normal
[Normal]
xilxBitgStart_Clk=xstvlg, virtexe, Verilog.t_bitFile, 1039259052, JTAG Clock
[STRATEGY-LIST]
Normal=True