tenths.veo

Xilinx ISE 官方源代码盘第七章 Part 2

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// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
tenths YourInstanceName (
	.Q(Q),
	.CLK(CLK),
	.Q_THRESH0(Q_THRESH0),
	.CE(CE),
	.AINIT(AINIT));

// INST_TAG_END ------ End INSTANTIATION Template ---------

// You must compile the wrapper file tenths.v when simulating
// the core, tenths. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "Coregen Users Guide".