stopwatch.syr

Xilinx ISE 官方源代码盘第七章 Part 2

Release 5.1.02i - xst F.25
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.
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--> Reading design: stopwatch.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Low Level Synthesis
  6) Final Report
     6.1) Device utilization summary
     6.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : stopwatch.prj
Input Format                       : VERILOG
Ignore Synthesis Constraint File   : NO
Verilog Search Path                : 
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : stopwatch
Output Format                      : NGC
Target Device                      : xcv300e-6bg432

---- Source Options
Top Module Name                    : stopwatch
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Complex Clock Enable Extraction    : YES
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Criterion             : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Top module area constraint         : 100
Top module allowed area overflow   : 5

---- Other Options
read_cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "stopwatch.prj"
Compiling include file "smallcntr.v"
Module <smallcntr> compiled
Compiling include file "cnt60.v"
Module <cnt60> compiled
Compiling include file "decode.v"
Module <decode> compiled
Compiling include file "hex2led.v"
Module <hex2led> compiled
Compiling include file "statmach.v"
Module <statmach> compiled
Compiling include file "tenths.v"
Module <tenths> compiled
Compiling include file "stopwatch.v"
Module <stopwatch> compiled
Compiling include file "C:/Xilinx/verilog/src/iSE/unisim_comp.v"
No errors in compilation

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analysis of file <stopwatch.prj> succeeded.
 
WARNING:Xst:878 - tenths.v line 82: Unrecognized directive. Ignoring.
 
Analyzing module <statmach>.
statmach.v line 26: Found FullParallel Case directive in module <statmach>.
Module <statmach> is correct for synthesis.
 
Analyzing module <tenths>.
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
 
Analyzing module <decode>.
Module <decode> is correct for synthesis.
 
Analyzing module <smallcntr>.
Module <smallcntr> is correct for synthesis.
 
Analyzing module <cnt60>.
Module <cnt60> is correct for synthesis.
 
Analyzing module <hex2led>.
Module <hex2led> is correct for synthesis.
 
Analyzing top module <stopwatch>.
Module <stopwatch> is correct for synthesis.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <statmach>.
    Related source file is statmach.v.
    Found finite state machine <FSM_0> for signal <current_state>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 11                                             |
    | Inputs             | 1                                              |
    | Outputs            | 2                                              |
    | Reset type         | asynchronous                                   |
    | Encoding           | automatic                                      |
    | State register     | d  flip-flops                                  |
    -----------------------------------------------------------------------
    Summary:
	inferred   1 Finite State Machine(s).
Unit <statmach> synthesized.


Synthesizing Unit <decode>.
    Related source file is decode.v.
    Found 16x10-bit ROM for signal <ONE_HOT>.
    Summary:
	inferred   1 ROM(s).
Unit <decode> synthesized.


Synthesizing Unit <smallcntr>.
    Related source file is smallcntr.v.
    Found 4-bit up counter for signal <QOUT>.
    Summary:
	inferred   1 Counter(s).
Unit <smallcntr> synthesized.


Synthesizing Unit <cnt60>.
    Related source file is cnt60.v.
Unit <cnt60> synthesized.


Synthesizing Unit <hex2led>.
    Related source file is hex2led.v.
    Found 16x7-bit ROM for signal <LED>.
    Summary:
	inferred   1 ROM(s).
Unit <hex2led> synthesized.


Synthesizing Unit <stopwatch>.
    Related source file is stopwatch.v.
WARNING:Xst:646 - Signal <strtstopinv> is assigned but never used.
Unit <stopwatch> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# ROMs                             : 3
  16x10-bit ROM                    : 1
  16x7-bit ROM                     : 2
# Counters                         : 2
  4-bit up counter                 : 2

=========================================================================

Optimizing FSM <FSM_0> with One-Hot encoding and d flip-flops.
=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: "tenths.ngo" is up to date.
Loading core <tenths> for timing and area information for instance <XCOUNTER>.

Library "C:/Xilinx/data/librtl.xst" Consulted

Optimizing unit <stopwatch> ...

Optimizing unit <statmach> ...

Optimizing unit <cnt60> ...

Mapping all equations...
Loading device for application Xst from file 'v300e.nph' in environment C:/Xilinx.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block stopwatch, actual ratio is 1.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Output File Name               : stopwatch.ngr
Top Level Output File Name         : stopwatch
Output Format                      : NGC
Optimization Criterion             : Speed
Keep Hierarchy                     : NO
Macro Generator                    : macro+

Design Statistics
# IOs                              : 27

Macro Statistics :
# ROMs                             : 3
#      16x10-bit ROM               : 1
#      16x7-bit ROM                : 2
# Counters                         : 2
#      4-bit up counter            : 2

Cell Usage :
# BELS                             : 76
#      GND                         : 2
#      LUT2                        : 1
#      LUT2_D                      : 1
#      LUT2_L                      : 1
#      LUT3                        : 4
#      LUT4                        : 40
#      LUT4_D                      : 1
#      LUT4_L                      : 3
#      MUXCY                       : 11
#      VCC                         : 1
#      XORCY                       : 11
# FlipFlops/Latches                : 20
#      FDC                         : 5
#      FDCE                        : 3
#      FDCPE                       : 8
#      FDE                         : 2
#      FDP                         : 1
#      FDPE                        : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 26
#      IBUF                        : 2
#      OBUF                        : 24
=========================================================================

Device utilization summary:
---------------------------

Selected Device : v300ebg432-6 

 Number of Slices:                      30  out of   3072     0%  
 Number of Slice Flip Flops:            20  out of   6144     0%  
 Number of 4 input LUTs:                51  out of   6144     0%  
 Number of bonded IOBs:                 26  out of    320     8%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
CLK                                | BUFGP                  | 20    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 6.955ns (Maximum Frequency: 143.781MHz)
   Minimum input arrival time before clock: 3.381ns
   Maximum output required time after clock: 8.902ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'CLK'
Delay:               6.955ns (Levels of Logic = 6)
  Source:            XCOUNTER/BU10
  Destination:       XCOUNTER/BU24
  Source Clock:      CLK rising
  Destination Clock: CLK rising

  Data Path: XCOUNTER/BU10 to XCOUNTER/BU24
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDPE:C->Q            11   0.992   1.840  BU10 (Q<0>)
     LUT4:I0->O            4   0.468   0.000  BU6 (N98)
     MUXCY:S->O            1   0.515   0.000  BU7 (N100)
     MUXCY:CI->O           1   0.058   0.000  BU12 (N105)
     MUXCY:CI->O           0   0.058   0.000  BU17 (N110)
     XORCY:CI->O           3   0.648   1.184  BU22 (N5)
     LUT4:I0->O            1   0.468   0.000  BU23 (N194)
     FDCE:D                    0.724          BU24
    ----------------------------------------
    Total                      6.955ns (3.931ns logic, 3.024ns route)
                                       (56.5% logic, 43.5% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'CLK'
Offset:              3.381ns (Levels of Logic = 2)
  Source:            STRTSTOP
  Destination:       MACHINE_current_state_FFD2
  Destination Clock: CLK rising

  Data Path: STRTSTOP to MACHINE_current_state_FFD2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             5   0.797   1.392  STRTSTOP_IBUF (STRTSTOP_IBUF)
     LUT3:I1->O            1   0.468   0.000  MACHINE_current_state_XX_FFd21 (MACHINE_current_state_XX_FFd2)
     FDC:D                     0.724          MACHINE_current_state_FFD2
    ----------------------------------------
    Total                      3.381ns (1.989ns logic, 1.392ns route)
                                       (58.8% logic, 41.2% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK'
Offset:              8.902ns (Levels of Logic = 2)
  Source:            sixty_msbcount_QOUT_1
  Destination:       TENSOUT<4>
  Source Clock:      CLK rising

  Data Path: sixty_msbcount_QOUT_1 to TENSOUT<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:C->Q           12   0.992   1.920  sixty_msbcount_QOUT_1 (sixty_msbcount_QOUT_1)
     LUT4:I1->O            1   0.468   0.920  msbled_Mrom_LED_inst_lut4_41 (TENSOUT_4_OBUF)
     OBUF:I->O                 4.602          TENSOUT_4_OBUF (TENSOUT<4>)
    ----------------------------------------
    Total                      8.902ns (6.062ns logic, 2.840ns route)
                                       (68.1% logic, 31.9% route)

=========================================================================
CPU : 3.98 / 4.96 s | Elapsed : 4.00 / 5.00 s
 
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Total memory usage is 66732 kilobytes