tenths.xco

Xilinx ISE 官方源代码盘第七章 Part 2

# Xilinx CORE Generator 4.1i
# Username = paulgl
# COREGenPath = d:\xilinx_e28\coregen
# ProjectPath = D:\xilinx_e28\ISEexamples\watchver
# ExpandedProjectPath = D:\xilinx_e28\ISEexamples\watchver
# OverwriteFiles = Default
SET BusFormat = BusFormatAngleBracket
SET SimulationOutputProducts = Verilog VHDL
SET XilinxFamily = Virtex
SET OutputOption = DesignFlow
SET DesignFlow = Verilog
SET FlowVendor = Foundation_iSE
SET FormalVerification = None
SELECT Binary_Counter Virtex Xilinx,_Inc. 3.0
CSET threshold_1_value = MAX
CSET threshold_early = true
CSET threshold_0_value = A
CSET synchronous_settings = none
CSET count_style = count_by_constant
CSET create_rpm = true
CSET threshold_options = registered
CSET count_by_value = 1
CSET load = false
CSET async_init_value = 1
CSET component_name = tenths
CSET sync_init_value = 0
CSET operation = up
CSET restrict_count = true
CSET ce_overrides = sync_controls_override_ce
CSET set_clear_priority = clear_overrides_set
CSET ce_override_for_load = false
CSET output_width = 4
CSET clock_enable = true
CSET asynchronous_settings = init
CSET threshold_1 = false
CSET threshold_0 = true
CSET load_sense = active_high
CSET count_to_value = A
GENERATE