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#COREGen Project File#Mon Jun 04 16:49:02 MDT 2001C_MUX_BIT_V1_0|Xilinx,\ Inc.|1.0=falsemult_gen_v3_0|Xilinx,\ Inc.|3.0=falsedesignflow=Verilogutsla_143s|CoreEl_MicroSystems|1.0=trueC_COUNTER_BINARY_V1_0|Xilinx,\ Inc.|1.0=falsexftwsi_ms|MemecCore|1.0=truevfft256|Xilinx,\ Inc.|1.0=truencoiqvht|Xilinx,\ Inc.|1.1=truexen_u3_atm_tx|Xentec,_Inc.|1.0=truekcmpipeVHT|Xilinx,\ Inc.|1.0=trueromrVHT|Xilinx,\ Inc.|1.0=truec2910a_mc|CAST_Inc.|1.0=truecorelibraryid=0delayVHT|Xilinx,\ Inc.|1.0=trueadreVHT|Xilinx,\ Inc.|1.0=truem8254|Virtual_IP_Group,_Inc|1.0=truesubreVHT|Xilinx,\ Inc.|1.0=trueoutputproducts=ImpNetlist;ASYSymbol;VerilogSim;VHDLSimreed_sol|Amphion,_Ltd.|1.0=truem8x8|Xilinx,\ Inc.|1.0=trueC_CIC_V1_0|Xilinx,\ Inc.|1.0=truekdcm_v1_0|Xilinx,\ Inc.|1.0=falsexlnx_PCI64v|Xilinx,\ Inc.|1.0=truec16550|CAST_Inc.|1.0=trueC_COMPARE_V3_0|Xilinx,\ Inc.|3.0=falseC_TWOS_COMP_V3_0|Xilinx,\ Inc.|3.0=falsexf_des|MemecCore|1.0=trueusb_heb|Inventra|1.0=trueC_GATE_BIT_V3_0|Xilinx,\ Inc.|3.0=falsepscVHT|Xilinx,\ Inc.|1.0=truegva_200|GV_&_Associates_Inc.|1.0=truemux2VHT|Xilinx,\ Inc.|1.0=trueC_SIN_COS_V2_0|Xilinx,\ Inc.|2.0=falsec80530|CAST_Inc.|1.0=trueusb_ssm|Inventra|1.0=truexf8250|MemecCore|1.0=truexf_rsenc|MemecCore|1.0=truemds_xf8256|MemecCore|1.0=trueC_REG_LD_V4_0|Xilinx,\ Inc.|4.0=truecselt_int_deint|CSELT_S.p.A|1.0=truecldl|CoreEl_MicroSystems|1.0=truesaddceVHT|Xilinx,\ Inc.|1.0=truedelta_ltcg|Deltatec|1.0=trueC_DIST_MEM_V3_0|Xilinx,\ Inc.|3.0=falsexen_jpeg|Xentec,_Inc.|1.0=truevfft64|Xilinx,\ Inc.|1.0=truesubrleVHT|Xilinx,\ Inc.|1.0=truexilinxsubfamily=Virtexusb_fsf|Inventra|1.0=truexlnx_pci64_dk|Xilinx,\ Inc.|1.0=truey2rgb|Perigee_LLC|1.0=truev8u|VAutomation|1.0=truepci32_s|Xilinx,\ Inc.|1.0=trueC_DA_FIR_V1_0|Xilinx,\ Inc.|1.0=falseC_GATE_BUS_V2_0|Xilinx,\ Inc.|2.0=falseC_MUX_SLICE_BUFT_V4_0|Xilinx,\ Inc.|4.0=trueasync_fifo_v2_0|Xilinx,\ Inc.|2.0=falseC_SHIFT_FD_V3_0|Xilinx,\ Inc.|3.0=falsemult_gen_v2_0|Xilinx,\ Inc.|2.0=falsem8259|Virtual_IP_Group,_Inc|1.0=truevtoolsd|Xilinx,\ Inc.|1.0=truem12x12|Xilinx,\ Inc.|1.0=trueC_MUX_SLICE_BUFE_V4_0|Xilinx,\ Inc.|4.0=trueoverwritefiles=Defaultmtif|Virtual_IP_Group,_Inc|1.0=trueC_ADDSUB_V4_0|Xilinx,\ Inc.|4.0=truesimulationoutputproducts=Verilog\ VHDLtsb16sVHT|Xilinx,\ Inc.|1.0=trueblkmemsp_v3_1|Xilinx,\ Inc.|3.1=truecmpsVHT|Xilinx,\ Inc.|1.0=truetsb32xVHT|Xilinx,\ Inc.|1.0=truevfft32_v1_0|Xilinx,\ Inc.|1.0=truecrc10|CoreEl_MicroSystems|1.0=trueC_MUX_SLICE_BUFT_V2_0|Xilinx,\ Inc.|2.0=falseregceVHT|Xilinx,\ Inc.|1.0=trueblkmemdp_v3_0|Xilinx,\ Inc.|3.0=falsetsb16xVHT|Xilinx,\ Inc.|1.0=trueC_GATE_BIT_BUS_V4_0|Xilinx,\ Inc.|4.0=trueutma|CoreEl_MicroSystems|1.0=trueC_COUNTER_BINARY_V4_0|Xilinx,\ Inc.|4.0=truemds_DVB|MemecCore|1.0=truecompact_uart|CAST_Inc.|1.0=truegva_250|GV_&_Associates_Inc.|1.0=truenmi_mcec|NMI_Electronics_Ltd.|1.0=trueC_COMPARE_V2_0|Xilinx,\ Inc.|2.0=falseC_TWOS_COMP_V2_0|Xilinx,\ Inc.|2.0=falseC_ACCUM_V3_0|Xilinx,\ Inc.|3.0=falsec16450|CAST_Inc.|1.0=truevfft1024v2|Xilinx,\ Inc.|2.0=truergb2y|Perigee_LLC|1.0=trueC_GATE_BIT_V2_0|Xilinx,\ Inc.|2.0=falseapplied_ima8|Applied\ Telecom,\ Inc.|1.0=truexlnx_PCI64s2|Xilinx,\ Inc.|1.0=truec2901|CAST_Inc.|1.0=trueapplied_ima32|Applied\ Telecom,\ Inc.|1.0=truedecode_8b10b_v2_0|Xilinx,\ Inc.|2.0=trueHDLC1_catalog|Xilinx,\ Inc.|1.0=truec8255a|CAST_Inc.|1.0=truexlnx_PCI32v|Xilinx,\ Inc.|1.0=trueC_REG_LD_V3_0|Xilinx,\ Inc.|3.0=falsesync_fifo_v2_0|Xilinx,\ Inc.|2.0=truec80530r|CAST_Inc.|1.0=truemac_v1_0|Xilinx,\ Inc.|1.0=falsesdram|NMI_Electronics_Ltd.|1.0=trueC_MUX_BUS_V3_0|Xilinx,\ Inc.|3.0=falseC_SHIFT_FD_V4_0|Xilinx,\ Inc.|4.0=trueclas|CoreEl_MicroSystems|1.0=truexdes|Xentec,_Inc.|1.0=truem16450|Virtual_IP_Group,_Inc|1.0=trueC_MEM_SP_BLOCK_V1_0|Xilinx,\ Inc.|1.0=falsemult_vgen_v2_0|Xilinx,\ Inc.|2.0=trueC_DIST_MEM_V2_0|Xilinx,\ Inc.|2.0=falsemux3VHT|Xilinx,\ Inc.|1.0=trueflip805x|Dolphin_Integration|1.0=trueenet_brd|CoreEl_MicroSystems|1.0=truecselt_descrambler|CSELT_S.p.A|1.0=truexf8255|MemecCore|1.0=trueC_GATE_BUS_V1_0|Xilinx,\ Inc.|1.0=falsexf_rsdec|MemecCore|1.0=trueC_REG_LD_V1_0|Xilinx,\ Inc.|1.0=falseasync_fifo_v1_0|Xilinx,\ Inc.|1.0=falseC_MUX_SLICE_BUFT_V3_0|Xilinx,\ Inc.|3.0=falsecselt_noisy|CSELT_S.p.A|1.0=truecselt_utopia_tx|CSELT_S.p.A|1.0=trueC_SHIFT_FD_V2_0|Xilinx,\ Inc.|2.0=falseC_SHIFT_RAM_V4_0|Xilinx,\ Inc.|4.0=trueC_DECODE_BINARY_V4_0|Xilinx,\ Inc.|4.0=trueformalverification=NonesdafirVHT|Xilinx,\ Inc.|1.0=trueC_MUX_SLICE_BUFE_V3_0|Xilinx,\ Inc.|3.0=falseC_ADDSUB_V3_0|Xilinx,\ Inc.|3.0=falseC_ACCUM_V4_0|Xilinx,\ Inc.|4.0=truexlnx_PCI32sII|Xilinx,\ Inc.|1.0=trueC_DA_FIR_V4_0|Xilinx,\ Inc.|4.0=falsecam_v1_0|Xilinx,\ Inc.|1.0=trueintegVHT|Xilinx,\ Inc.|1.0=trueblkmemdp_v3_1|Xilinx,\ Inc.|3.1=truebusformat=BusFormatAngleBracketxlnx_rsenc|Xilinx,\ Inc.|1.0=truefifosyncVHT|Xilinx,\ Inc.|1.0=falsecrc32|CoreEl_MicroSystems|1.0=truecselt_scrambler|CSELT_S.p.A|1.0=truexen_x3des|Xentec,_Inc.|1.0=trueC_MUX_SLICE_BUFT_V1_0|Xilinx,\ Inc.|1.0=falseC_GATE_BIT_BUS_V3_0|Xilinx,\ Inc.|3.0=falseC_COUNTER_BINARY_V3_0|Xilinx,\ Inc.|3.0=falseC_SHIFT_RAM_V2_0|Xilinx,\ Inc.|2.0=falseacc2sVHT|Xilinx,\ Inc.|1.0=trueiss_adpcm|Amphion,_Ltd.|1.0=trueC_DIST_MEM_V4_1|Xilinx,\ Inc.|4.1=trueC_MUX_BUS_V4_0|Xilinx,\ Inc.|4.0=trueC_COMPARE_V1_0|Xilinx,\ Inc.|1.0=falseC_TWOS_COMP_V1_0|Xilinx,\ Inc.|1.0=falsecs1100|CoreEl_MicroSystems|1.0=trueC_ACCUM_V2_0|Xilinx,\ Inc.|2.0=falsec8051|CAST_Inc.|1.0=trueC_GATE_BIT_V1_0|Xilinx,\ Inc.|1.0=falsevfft1024|Xilinx,\ Inc.|1.0=truedecode_8b10b_v1_0|Xilinx,\ Inc.|1.0=falsemac_v1_1|Xilinx,\ Inc.|1.1=trueC_REG_FD_V4_0|Xilinx,\ Inc.|4.0=trueencode_8b10b_v1_0|Xilinx,\ Inc.|1.0=trueC_GATE_BIT_BUS_V1_0|Xilinx,\ Inc.|1.0=falsem8237|Virtual_IP_Group,_Inc|1.0=truemult_gen_v3_1|Xilinx,\ Inc.|3.1=truecselt_utopia_rx|CSELT_S.p.A|1.0=trueC_REG_LD_V2_0|Xilinx,\ Inc.|2.0=falsemagicnumber=-1172307782blkmemv2sp_v2_0|Xilinx,\ Inc.|2.0=truec6850|CAST_Inc.|1.0=truesync_fifo_v1_0|Xilinx,\ Inc.|1.0=falsecombfiltVHT|Xilinx,\ Inc.|1.0=truedividervht|Xilinx,\ Inc.|2.0=trueC_MUX_BUS_V2_0|Xilinx,\ Inc.|2.0=falseflowvendor=Foundation_iSExlnx_rsdec|Xilinx,\ Inc.|1.0=trueadrleVHT|Xilinx,\ Inc.|1.0=truespartan_xl|Xilinx,\ Inc.|1.0=trueblkmemsp_v3_0|Xilinx,\ Inc.|3.0=falsemds_hdlc|MemecCore|1.0=trueC_DIST_MEM_V1_0|Xilinx,\ Inc.|1.0=falsemult_vgen_v1_0|Xilinx,\ Inc.|1.0=falsem8255|Virtual_IP_Group,_Inc|1.0=trueoutputoption=DesignFlowC_DA_FIR_V5_0|Xilinx,\ Inc.|5.0=truec8251|CAST_Inc.|1.0=truerapid200|Rapid\ Prototypes,\ Inc.|1.0=trueC_REG_FD_V2_0|Xilinx,\ Inc.|2.0=falsecselt_arbiter|CSELT_S.p.A|1.0=trueC_MEM_DP_BLOCK_V1_0|Xilinx,\ Inc.|1.0=falsefileversion=3c8259a|CAST_Inc.|1.0=trueC_MUX_BIT_V4_0|Xilinx,\ Inc.|4.0=truemulVHT|Xilinx,\ Inc.|1.0=truersde|Amphion,_Ltd.|1.0=trueC_DDS_V2_0|Xilinx,\ Inc.|2.0=falseC_SHIFT_FD_V1_0|Xilinx,\ Inc.|1.0=falsexen_u3_atm_rx|Xentec,_Inc.|1.0=truemds_xf8279|MemecCore|1.0=trueC_SHIFT_RAM_V3_0|Xilinx,\ Inc.|3.0=falsemux4VHT|Xilinx,\ Inc.|1.0=truepdafirVHT|Xilinx,\ Inc.|1.0=trueC_DECODE_BINARY_V3_0|Xilinx,\ Inc.|3.0=falsegva_220|GV_&_Associates_Inc.|1.0=trueC_MUX_SLICE_BUFE_V2_0|Xilinx,\ Inc.|2.0=falseC_ADDSUB_V2_0|Xilinx,\ Inc.|2.0=falseaddsVHT|Xilinx,\ Inc.|1.0=trueC_GATE_BUS_V4_0|Xilinx,\ Inc.|4.0=trueC_DA_FIR_V3_0|Xilinx,\ Inc.|3.0=falsexen_utopia3t|Xentec,_Inc.|1.0=trueC_SIN_COS_V2_1|Xilinx,\ Inc.|2.1=falsexftwsi|MemecCore|1.0=trueC_MUX_BIT_V2_0|Xilinx,\ Inc.|2.0=falsevfft16v2|Xilinx,\ Inc.|2.0=trueC_GATE_BIT_BUS_V2_0|Xilinx,\ Inc.|2.0=falsekcmVHT|Xilinx,\ Inc.|1.0=trueC_COUNTER_BINARY_V2_0|Xilinx,\ Inc.|2.0=falseC_SHIFT_RAM_V1_0|Xilinx,\ Inc.|1.0=falseC_DECODE_BINARY_V1_0|Xilinx,\ Inc.|1.0=falsedpramVHT|Xilinx,\ Inc.|1.0=truearc32risc|ARC\ Cores|1.0=trueC_ACCUM_V1_0|Xilinx,\ Inc.|1.0=falseppp8_hdlc|CoreEl_MicroSystems|1.0=truecselt_viterbid|CSELT_S.p.A|1.0=trueADPCM32_catalog|Xilinx,\ Inc.|1.0=trueC_REG_FD_V3_0|Xilinx,\ Inc.|3.0=falsekdcm_v2_0|Xilinx,\ Inc.|2.0=trueC_COMPARE_V4_0|Xilinx,\ Inc.|4.0=trueC_TWOS_COMP_V4_0|Xilinx,\ Inc.|4.0=truesyncramVHT|Xilinx,\ Inc.|1.0=trueC_DDS_V3_0|Xilinx,\ Inc.|3.0=truetrigtablvht|Xilinx,\ Inc.|1.0=falsem16550a|Virtual_IP_Group,_Inc|1.0=trueC_MUX_BUS_V1_0|Xilinx,\ Inc.|1.0=falsencovht|Xilinx,\ Inc.|1.1=truesqrootVHT|Xilinx,\ Inc.|1.0=truecanbus|SICAN_Microelectronics|1.0=trueC_GATE_BIT_V4_0|Xilinx,\ Inc.|4.0=trueblkmemv2dp_v2_0|Xilinx,\ Inc.|2.0=truelockprojectprops=falsecselt_convenc|CSELT_S.p.A|1.0=truevfft256v2|Xilinx,\ Inc.|2.0=trueips|VAutomation|1.0=trueC_SIN_COS_V3_0|Xilinx,\ Inc.|3.0=truegva_270|GV_&_Associates_Inc.|1.0=truexen_utopia3r|Xentec,_Inc.|1.0=trueC_BIT_CORRELATOR_V2_0|Xilinx,\ Inc.|2.0=truevfft16|Xilinx,\ Inc.|1.0=trueC_REG_FD_V1_0|Xilinx,\ Inc.|1.0=falseHDLC32_catalog|Xilinx,\ Inc.|1.0=trueC_MUX_BIT_V3_0|Xilinx,\ Inc.|3.0=falseutsla|CoreEl_MicroSystems|1.0=truexilinxfamily=VirtexC_DIST_MEM_V4_0|Xilinx,\ Inc.|4.0=falseC_DECODE_BINARY_V2_0|Xilinx,\ Inc.|2.0=falsevfft64v2|Xilinx,\ Inc.|2.0=trueC_MUX_SLICE_BUFE_V1_0|Xilinx,\ Inc.|1.0=trueusb_lsf|Inventra|1.0=trueC_ADDSUB_V1_0|Xilinx,\ Inc.|1.0=falseC_GATE_BUS_V3_0|Xilinx,\ Inc.|3.0=falseasync_fifo_v3_0|Xilinx,\ Inc.|3.0=truegva100|GV_&_Associates_Inc.|1.0=true⌨️ 快捷键说明
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