prescale_counter.twr

Xilinx ISE 官方源代码盘第七章 Part 2

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Release 6.2i Trace G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

D:/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml prescale_counter
prescale_counter.ncd -o prescale_counter.twr prescale_counter.pcf


Design file:              prescale_counter.ncd
Physical constraint file: prescale_counter.pcf
Device,speed:             xc2s200,-6 (PRODUCTION 1.27 2003-12-13)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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WARNING:Timing:2666 - Constraint ignored: PATH "FROM U_CLK TO D_CLK"  TIG ;
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.

================================================================================
Timing constraint: TS_J_TO_J = MAXDELAY FROM TIMEGRP "J_CLK" TO TIMEGRP "J_CLK" 30 nS  ; 

 7091 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
 Maximum delay is  12.225ns.
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================================================================================
Timing constraint: TS_U_TO_J = MAXDELAY FROM TIMEGRP "U_CLK" TO TIMEGRP "J_CLK" 15 nS  ; 

 18 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
 Maximum delay is   5.945ns.
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================================================================================
Timing constraint: TS_U_TO_U = MAXDELAY FROM TIMEGRP "U_CLK" TO TIMEGRP "U_CLK" 15 nS  ; 

 1 item analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
 Maximum delay is   2.634ns.
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================================================================================
Timing constraint: PATH "FROM U_CLK TO D_CLK"  TIG ;

 0 items analyzed, 0 timing errors detected.
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================================================================================
Timing constraint: PATH "FROM J_CLK TO D_CLK"  TIG ;

 2766 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
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================================================================================
Timing constraint: PATH "FROM D_CLK TO J_CLK"  TIG ;

 1145 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
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All constraints were met.


Data Sheet report:
-----------------
No constraints were found to generate data for the Data Sheet Report section.
Use the Advanced Analysis (-a) option or generate global constraints for each
clock, its pad to setup and clock to pad paths, and a pad to pad constraint.


Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover 11021 paths, 0 nets, and 2010 connections

Design statistics:
   Minimum period:  12.225ns (Maximum frequency:  81.800MHz)
   Maximum path delay from/to any node:  12.225ns


Analysis completed Fri Jul 09 17:16:30 2004
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Peak Memory Usage: 51 MB