prescale_counter_timesim.v

Xilinx ISE 官方源代码盘第七章 Part1

    .I(\counter<10>/OD ),
    .O(\counter<10>/OUTMUX )
  );
  X_BUF \counter<10>/GTS_OR  (
    .I(GTS),
    .O(\counter<10>/TORGTS )
  );
  X_INV \counter<10>/ENABLEINV  (
    .I(\counter<10>/TORGTS ),
    .O(\counter<10>/ENABLE )
  );
  X_TRI counter_10_OBUF (
    .I(\counter<10>/OUTMUX ),
    .CTL(\counter<10>/ENABLE ),
    .O(counter[10])
  );
  X_OPAD \counter<10>/PAD  (
    .PAD(counter[10])
  );
  X_BUF \counter<11>/OMUX  (
    .I(counter_11),
    .O(\counter<11>/OD )
  );
  X_BUF \counter<11>/OUTMUX_95  (
    .I(\counter<11>/OD ),
    .O(\counter<11>/OUTMUX )
  );
  X_BUF \counter<11>/GTS_OR  (
    .I(GTS),
    .O(\counter<11>/TORGTS )
  );
  X_INV \counter<11>/ENABLEINV  (
    .I(\counter<11>/TORGTS ),
    .O(\counter<11>/ENABLE )
  );
  X_TRI counter_11_OBUF (
    .I(\counter<11>/OUTMUX ),
    .CTL(\counter<11>/ENABLE ),
    .O(counter[11])
  );
  X_OPAD \counter<11>/PAD  (
    .PAD(counter[11])
  );
  X_BUF \counter<12>/OMUX  (
    .I(counter_12),
    .O(\counter<12>/OD )
  );
  X_BUF \counter<12>/OUTMUX_96  (
    .I(\counter<12>/OD ),
    .O(\counter<12>/OUTMUX )
  );
  X_BUF \counter<12>/GTS_OR  (
    .I(GTS),
    .O(\counter<12>/TORGTS )
  );
  X_INV \counter<12>/ENABLEINV  (
    .I(\counter<12>/TORGTS ),
    .O(\counter<12>/ENABLE )
  );
  X_TRI counter_12_OBUF (
    .I(\counter<12>/OUTMUX ),
    .CTL(\counter<12>/ENABLE ),
    .O(counter[12])
  );
  X_OPAD \counter<12>/PAD  (
    .PAD(counter[12])
  );
  X_BUF \counter<20>/OMUX  (
    .I(counter_20),
    .O(\counter<20>/OD )
  );
  X_BUF \counter<20>/OUTMUX_97  (
    .I(\counter<20>/OD ),
    .O(\counter<20>/OUTMUX )
  );
  X_BUF \counter<20>/GTS_OR  (
    .I(GTS),
    .O(\counter<20>/TORGTS )
  );
  X_INV \counter<20>/ENABLEINV  (
    .I(\counter<20>/TORGTS ),
    .O(\counter<20>/ENABLE )
  );
  X_TRI counter_20_OBUF (
    .I(\counter<20>/OUTMUX ),
    .CTL(\counter<20>/ENABLE ),
    .O(counter[20])
  );
  X_OPAD \counter<20>/PAD  (
    .PAD(counter[20])
  );
  X_BUF \counter<13>/OMUX  (
    .I(counter_13),
    .O(\counter<13>/OD )
  );
  X_BUF \counter<13>/OUTMUX_98  (
    .I(\counter<13>/OD ),
    .O(\counter<13>/OUTMUX )
  );
  X_BUF \counter<13>/GTS_OR  (
    .I(GTS),
    .O(\counter<13>/TORGTS )
  );
  X_INV \counter<13>/ENABLEINV  (
    .I(\counter<13>/TORGTS ),
    .O(\counter<13>/ENABLE )
  );
  X_TRI counter_13_OBUF (
    .I(\counter<13>/OUTMUX ),
    .CTL(\counter<13>/ENABLE ),
    .O(counter[13])
  );
  X_OPAD \counter<13>/PAD  (
    .PAD(counter[13])
  );
  X_BUF \counter<21>/OMUX  (
    .I(counter_21),
    .O(\counter<21>/OD )
  );
  X_BUF \counter<21>/OUTMUX_99  (
    .I(\counter<21>/OD ),
    .O(\counter<21>/OUTMUX )
  );
  X_BUF \counter<21>/GTS_OR  (
    .I(GTS),
    .O(\counter<21>/TORGTS )
  );
  X_INV \counter<21>/ENABLEINV  (
    .I(\counter<21>/TORGTS ),
    .O(\counter<21>/ENABLE )
  );
  X_TRI counter_21_OBUF (
    .I(\counter<21>/OUTMUX ),
    .CTL(\counter<21>/ENABLE ),
    .O(counter[21])
  );
  X_OPAD \counter<21>/PAD  (
    .PAD(counter[21])
  );
  X_BUF \counter<14>/OMUX  (
    .I(counter_14),
    .O(\counter<14>/OD )
  );
  X_BUF \counter<14>/OUTMUX_100  (
    .I(\counter<14>/OD ),
    .O(\counter<14>/OUTMUX )
  );
  X_BUF \counter<14>/GTS_OR  (
    .I(GTS),
    .O(\counter<14>/TORGTS )
  );
  X_INV \counter<14>/ENABLEINV  (
    .I(\counter<14>/TORGTS ),
    .O(\counter<14>/ENABLE )
  );
  X_TRI counter_14_OBUF (
    .I(\counter<14>/OUTMUX ),
    .CTL(\counter<14>/ENABLE ),
    .O(counter[14])
  );
  X_OPAD \counter<14>/PAD  (
    .PAD(counter[14])
  );
  X_BUF \counter<22>/OMUX  (
    .I(counter_22),
    .O(\counter<22>/OD )
  );
  X_BUF \counter<22>/OUTMUX_101  (
    .I(\counter<22>/OD ),
    .O(\counter<22>/OUTMUX )
  );
  X_BUF \counter<22>/GTS_OR  (
    .I(GTS),
    .O(\counter<22>/TORGTS )
  );
  X_INV \counter<22>/ENABLEINV  (
    .I(\counter<22>/TORGTS ),
    .O(\counter<22>/ENABLE )
  );
  X_TRI counter_22_OBUF (
    .I(\counter<22>/OUTMUX ),
    .CTL(\counter<22>/ENABLE ),
    .O(counter[22])
  );
  X_OPAD \counter<22>/PAD  (
    .PAD(counter[22])
  );
  X_BUF \counter<30>/OMUX  (
    .I(counter_30),
    .O(\counter<30>/OD )
  );
  X_BUF \counter<30>/OUTMUX_102  (
    .I(\counter<30>/OD ),
    .O(\counter<30>/OUTMUX )
  );
  X_BUF \counter<30>/GTS_OR  (
    .I(GTS),
    .O(\counter<30>/TORGTS )
  );
  X_INV \counter<30>/ENABLEINV  (
    .I(\counter<30>/TORGTS ),
    .O(\counter<30>/ENABLE )
  );
  X_TRI counter_30_OBUF (
    .I(\counter<30>/OUTMUX ),
    .CTL(\counter<30>/ENABLE ),
    .O(counter[30])
  );
  X_OPAD \counter<30>/PAD  (
    .PAD(counter[30])
  );
  X_BUF \counter<15>/OMUX  (
    .I(counter_15),
    .O(\counter<15>/OD )
  );
  X_BUF \counter<15>/OUTMUX_103  (
    .I(\counter<15>/OD ),
    .O(\counter<15>/OUTMUX )
  );
  X_BUF \counter<15>/GTS_OR  (
    .I(GTS),
    .O(\counter<15>/TORGTS )
  );
  X_INV \counter<15>/ENABLEINV  (
    .I(\counter<15>/TORGTS ),
    .O(\counter<15>/ENABLE )
  );
  X_TRI counter_15_OBUF (
    .I(\counter<15>/OUTMUX ),
    .CTL(\counter<15>/ENABLE ),
    .O(counter[15])
  );
  X_OPAD \counter<15>/PAD  (
    .PAD(counter[15])
  );
  X_BUF \counter<23>/OMUX  (
    .I(counter_23),
    .O(\counter<23>/OD )
  );
  X_BUF \counter<23>/OUTMUX_104  (
    .I(\counter<23>/OD ),
    .O(\counter<23>/OUTMUX )
  );
  X_BUF \counter<23>/GTS_OR  (
    .I(GTS),
    .O(\counter<23>/TORGTS )
  );
  X_INV \counter<23>/ENABLEINV  (
    .I(\counter<23>/TORGTS ),
    .O(\counter<23>/ENABLE )
  );
  X_TRI counter_23_OBUF (
    .I(\counter<23>/OUTMUX ),
    .CTL(\counter<23>/ENABLE ),
    .O(counter[23])
  );
  X_OPAD \counter<23>/PAD  (
    .PAD(counter[23])
  );
  X_BUF \counter<31>/OMUX  (
    .I(counter_31),
    .O(\counter<31>/OD )
  );
  X_BUF \counter<31>/OUTMUX_105  (
    .I(\counter<31>/OD ),
    .O(\counter<31>/OUTMUX )
  );
  X_BUF \counter<31>/GTS_OR  (
    .I(GTS),
    .O(\counter<31>/TORGTS )
  );
  X_INV \counter<31>/ENABLEINV  (
    .I(\counter<31>/TORGTS ),
    .O(\counter<31>/ENABLE )
  );
  X_TRI counter_31_OBUF (
    .I(\counter<31>/OUTMUX ),
    .CTL(\counter<31>/ENABLE ),
    .O(counter[31])
  );
  X_OPAD \counter<31>/PAD  (
    .PAD(counter[31])
  );
  X_BUF \counter<16>/OMUX  (
    .I(counter_16),
    .O(\counter<16>/OD )
  );
  X_BUF \counter<16>/OUTMUX_106  (
    .I(\counter<16>/OD ),
    .O(\counter<16>/OUTMUX )
  );
  X_BUF \counter<16>/GTS_OR  (
    .I(GTS),
    .O(\counter<16>/TORGTS )
  );
  X_INV \counter<16>/ENABLEINV  (
    .I(\counter<16>/TORGTS ),
    .O(\counter<16>/ENABLE )
  );
  X_TRI counter_16_OBUF (
    .I(\counter<16>/OUTMUX ),
    .CTL(\counter<16>/ENABLE ),
    .O(counter[16])
  );
  X_OPAD \counter<16>/PAD  (
    .PAD(counter[16])
  );
  X_BUF \counter<24>/OMUX  (
    .I(counter_24),
    .O(\counter<24>/OD )
  );
  X_BUF \counter<24>/OUTMUX_107  (
    .I(\counter<24>/OD ),
    .O(\counter<24>/OUTMUX )
  );
  X_BUF \counter<24>/GTS_OR  (
    .I(GTS),
    .O(\counter<24>/TORGTS )
  );
  X_INV \counter<24>/ENABLEINV  (
    .I(\counter<24>/TORGTS ),
    .O(\counter<24>/ENABLE )
  );
  X_TRI counter_24_OBUF (
    .I(\counter<24>/OUTMUX ),
    .CTL(\counter<24>/ENABLE ),
    .O(counter[24])
  );
  X_OPAD \counter<24>/PAD  (
    .PAD(counter[24])
  );
  X_BUF \counter<17>/OMUX  (
    .I(counter_17),
    .O(\counter<17>/OD )
  );
  X_BUF \counter<17>/OUTMUX_108  (
    .I(\counter<17>/OD ),
    .O(\counter<17>/OUTMUX )
  );
  X_BUF \counter<17>/GTS_OR  (
    .I(GTS),
    .O(\counter<17>/TORGTS )
  );
  X_INV \counter<17>/ENABLEINV  (
    .I(\counter<17>/TORGTS ),
    .O(\counter<17>/ENABLE )
  );
  X_TRI counter_17_OBUF (
    .I(\counter<17>/OUTMUX ),
    .CTL(\counter<17>/ENABLE ),
    .O(counter[17])
  );
  X_OPAD \counter<17>/PAD  (
    .PAD(counter[17])
  );
  X_OR2 \counter_2/FFX/RSTOR  (
    .I0(\counter_2/SRMUX_OUTPUTNOT ),
    .I1(GSR),
    .O(\counter_2/FFX/RST )
  );
  X_FF counter_2_109 (
    .I(Madd__n0001_inst_lut2_0),
    .CE(_n0002),
    .CLK(clk_BUFGP),
    .SET(GND),
    .RST(\counter_2/FFX/RST ),
    .O(counter_2)
  );
  X_OR2 \counter_18/FFY/RSTOR  (
    .I0(\counter_18/SRMUX_OUTPUTNOT ),
    .I1(GSR),
    .O(\counter_18/FFY/RST )
  );
  X_FF counter_19_110 (
    .I(_n0001[17]),
    .CE(_n0002),
    .CLK(clk_BUFGP),
    .SET(GND),
    .RST(\counter_18/FFY/RST ),
    .O(counter_19)
  );
  X_OR2 \counter_20/FFY/RSTOR  (
    .I0(\counter_20/SRMUX_OUTPUTNOT ),
    .I1(GSR),
    .O(\counter_20/FFY/RST )
  );
  X_FF counter_21_111 (
    .I(_n0001[19]),
    .CE(_n0002),
    .CLK(clk_BUFGP),
    .SET(GND),
    .RST(\counter_20/FFY/RST ),
    .O(counter_21)
  );
  X_OR2 \counter_26/FFY/RSTOR  (
    .I0(\counter_26/SRMUX_OUTPUTNOT ),
    .I1(GSR),
    .O(\counter_26/FFY/RST )
  );
  X_FF counter_27_112 (
    .I(_n0001[25]),
    .CE(_n00021_1),
    .CLK(clk_BUFGP),
    .SET(GND),
    .RST(\counter_26/FFY/RST ),
    .O(counter_27)
  );
  X_OR2 \counter_22/FFY/RSTOR  (
    .I0(\counter_22/SRMUX_OUTPUTNOT ),
    .I1(GSR),
    .O(\counter_22/FFY/RST )
  );
  X_FF counter_23_113 (
    .I(_n0001[21]),
    .CE(_n0002),
    .CLK(clk_BUFGP),
    .SET(GND),
    .RST(\counter_22/FFY/RST ),
    .O(counter_23)
  );
  X_OR2 \counter_25/FFY/RSTOR  (
    .I0(\counter_25/SRMUX_OUTPUTNOT ),
    .I1(GSR),
    .O(\counter_25/FFY/RST )
  );
  X_FF counter_25_114 (
    .I(_n0001[23]),
    .CE(_n00021_1),
    .CLK(clk_BUFGP),
    .SET(GND),
    .RST(\counter_25/FFY/RST ),
    .O(counter_25)
  );
  X_OR2 \counter_16/FFY/RSTOR  (
    .I0(\counter_16/SRMUX_OUTPUTNOT ),
    .I1(GSR),
    .O(\counter_16/FFY/RST )
  );
  X_FF counter_17_115 (
    .I(_n0001[15]),
    .CE(_n0002),
    .CLK(clk_BUFGP),
    .SET(GND),
    .RST(\counter_16/FFY/RST ),
    .O(counter_17)
  );
  X_OR2 \counter_16/FFX/RSTOR  (
    .I0(\counter_16/SRMUX_OUTPUTNOT ),
    .I1(GSR),
    .O(\counter_16/FFX/RST )
  );
  X_FF counter_16_116 (
    .I(_n0001[14]),
    .CE(_n0002),
    .CLK(clk_BUFGP),
    .SET(GND),
    .RST(\counter_16/FFX/RST ),
    .O(counter_16)
  );
  X_OR2 \counter_28/FFY/RSTOR  (
    .I0(\counter_28/SRMUX_OUTPUTNOT ),
    .I1(GSR),
    .O(\counter_28/FFY/RST )
  );
  X_FF counter_29_117 (
    .I(_n0001[27]),
    .CE(_n00021_1),
    .CLK(clk_BUFGP),
    .SET(GND),
    .RST(\counter_28/FFY/RST ),
    .O(counter_29)
  );
  X_OR2 \counter_18/FFX/RSTOR  (
    .I0(\counter_18/SRMUX_OUTPUTNOT ),
    .I1(GSR),
    .O(\counter_18/FFX/RST )
  );
  X_FF counter_18_118 (
    .I(_n0001[16]),
    .CE(_n0002),
    .CLK(clk_BUFGP),
    .SET(GND),
    .RST(\counter_18/FFX/RST ),
    .O(counter_18)
  );
  X_OR2 \counter_20/FFX/RSTOR  (
    .I0(\counter_20/SRMUX_OUTPUTNOT ),
    .I1(GSR),
    .O(\counter_20/FFX/RST )
  );
  X_FF counter_20_119 (
    .I(_n0001[18]),
    .CE(_n0002),
    .CLK(clk_BUFGP),
    .SET(GND),
    .RST(\counter_20/FFX/RST ),
    .O(counter_20)
  );
  X_OR2 \counter_22/FFX/RSTOR  (
    .I0(\counter_22/SRMUX_OUTPUTNOT ),
    .I1(GSR),
    .O(\counter_22/FFX/RST )
  );
  X_FF counter_22_120 (
    .I(_n0001[20]),
    .CE(_n0002),
    .CLK(clk_BUFGP),
    .SET(GND),
    .RST(\counter_22/FFX/RST ),
    .O(counter_22)
  );
  X_OR2 \counter_2/FFY/RSTOR  (
    .I0(\counter_2/SRMUX_OUTPUTNOT ),
    .I1(GSR),
    .O(\counter_2/FFY/RST )
  );
  X_FF counter_10_121 (
    .I(_n0001[8]),
    .CE(_n0002),
    .CLK(clk_BUFGP),
    .SET(GND),
    .RST(\counter_2/FFY/RST ),
    .O(counter_10)
  );
  X_OR2 \counter_26/FFX/RSTOR  (
    .I0(\counter_26/SRMUX_OUTPUTNOT ),
    .I1(GSR),
    .O(\counter_26/FFX/RST )
  );
  X_FF counter_26_122 (
    .I(_n0001[24]),
    .CE(_n00021_1),
    .CLK(clk_BUFGP),
    .SET(GND),
    .RST(\counter_26/FFX/RST ),
    .O(counter_26)
  );
  X_OR2 \counter_28/FFX/RSTOR  (
    .I0(\counter_28/SRMUX_OUTPUTNOT ),
    .I1(GSR),
    .O(\counter_28/FFX/RST )
  );
  X_FF counter_28_123 (
    .I(_n0001[26]),
    .CE(_n00021_1),
    .CLK(clk_BUFGP),
    .SET(GND),
    .RST(\counter_28/FFX/RST ),
    .O(counter_28)
  );
  X_OR2 \counter_0/FFY/RSTOR  (
    .I0(\counter_0/SRMUX_OUTPUTNOT ),
    .I1(GSR),
    .O(\counter_0/FFY/RST )
  );
  X_FF counter_1_124 (
    .I(_n0000[1]),
    .CE(VCC),
    .CLK(clk_BUFGP),
    .SET(GND),
    .RST(\counter_0/FFY/RST ),
    .O(counter_1)
  );
  X_OR2 \counter_0/FFX/RSTOR  (
    .I0(\counter_0/SRMUX_OUTPUTNOT ),
    .I1(GSR),
    .O(\counter_0/FFX/RST )
  );
  X_FF counter_0_125 (
    .I(\counter_0/BXMUXNOT ),
    .CE(VCC),
    .CLK(clk_BUFGP),
    .SET(GND),
    .RST(\counter_0/FFX/RST ),
    .O(counter_0)
  );
  X_CKBUF \clk/BUF  (
    .I(clk),
    .O(\clk_BUFGP/IBUFG )
  );
  X_IPAD \clk/PAD  (
    .PAD(clk)
  );
  X_CKBUF \clk_BUFGP/BUFG/BUF  (
    .I(\clk_BUFGP/IBUFG ),
    .O(clk_BUFGP)
  );
  X_BUF \PWR_VCC_0/XUSED  (
    .I(\PWR_VCC_0/FROM ),
    .O(GLOBAL_LOGIC1)
  );
  defparam \PWR_VCC_0/F .INIT = 16'hFFFF;
  X_LUT4 \PWR_VCC_0/F  (
    .ADR0(VCC),
    .ADR1(VCC),
    .ADR2(VCC),
    .ADR3(VCC),
    .O(\PWR_VCC_0/FROM )
  );
  X_ONE NlwBlock_prescale_counter_VCC (
    .O(VCC)
  );
  X_ZERO NlwBlock_prescale_counter_GND (
    .O(GND)
  );
  X_PD NGD2VER_PD_00F39530 (.O (GSR) );
  X_PD NGD2VER_PD_00F39548 (.O (GTS) );
endmodule