prescale_counter_timesim.v

Xilinx ISE 官方源代码盘第七章 Part1

    .O(\counter_0/SRMUX_OUTPUTNOT )
  );
  X_INV \counter_0/BXMUX  (
    .I(counter_0),
    .O(\counter_0/BXMUXNOT )
  );
  defparam \Madd__n0000_Mxor_Result<1>_Result1 .INIT = 16'h5A5A;
  X_LUT4 \Madd__n0000_Mxor_Result<1>_Result1  (
    .ADR0(counter_0),
    .ADR1(VCC),
    .ADR2(counter_1),
    .ADR3(VCC),
    .O(_n0000[1])
  );
  X_INV \counter_24/SRMUX  (
    .I(reset_IBUF),
    .O(\counter_24/SRMUX_OUTPUTNOT )
  );
  X_BUF \counter_24/YUSED  (
    .I(\counter_24/GROM ),
    .O(_n00021_1)
  );
  defparam _n00021_1_55.INIT = 16'hAA00;
  X_LUT4 _n00021_1_55 (
    .ADR0(counter_1),
    .ADR1(VCC),
    .ADR2(VCC),
    .ADR3(counter_0),
    .O(\counter_24/GROM )
  );
  X_OR2 \counter_24/FFY/RSTOR  (
    .I0(\counter_24/SRMUX_OUTPUTNOT ),
    .I1(GSR),
    .O(\counter_24/FFY/RST )
  );
  X_FF counter_24_56 (
    .I(_n0001[22]),
    .CE(_n00021_1),
    .CLK(clk_BUFGP),
    .SET(GND),
    .RST(\counter_24/FFY/RST ),
    .O(counter_24)
  );
  X_INV \counter_2/SRMUX  (
    .I(reset_IBUF),
    .O(\counter_2/SRMUX_OUTPUTNOT )
  );
  X_BUF \counter_2/YUSED  (
    .I(\counter_2/GROM ),
    .O(_n0002)
  );
  X_BUF \counter_2/XUSED  (
    .I(\counter_2/FROM ),
    .O(GLOBAL_LOGIC0)
  );
  defparam _n00021.INIT = 16'h8888;
  X_LUT4 _n00021 (
    .ADR0(counter_0),
    .ADR1(counter_1),
    .ADR2(VCC),
    .ADR3(VCC),
    .O(\counter_2/GROM )
  );
  defparam \counter_2/F .INIT = 16'h0000;
  X_LUT4 \counter_2/F  (
    .ADR0(VCC),
    .ADR1(VCC),
    .ADR2(VCC),
    .ADR3(VCC),
    .O(\counter_2/FROM )
  );
  X_BUF \counter_30/CYINIT_57  (
    .I(Madd__n0001_inst_cy_27),
    .O(\counter_30/CYINIT )
  );
  X_INV \counter_30/SRMUX  (
    .I(reset_IBUF),
    .O(\counter_30/SRMUX_OUTPUTNOT )
  );
  X_XOR2 Madd__n0001_inst_sum_29 (
    .I0(Madd__n0001_inst_cy_28),
    .I1(counter_31_rt),
    .O(_n0001[29])
  );
  defparam counter_31_rt_58.INIT = 16'hF0F0;
  X_LUT4 counter_31_rt_58 (
    .ADR0(VCC),
    .ADR1(VCC),
    .ADR2(counter_31),
    .ADR3(VCC),
    .O(counter_31_rt)
  );
  defparam \counter_30/F .INIT = 16'hCCCC;
  X_LUT4 \counter_30/F  (
    .ADR0(VCC),
    .ADR1(counter_30),
    .ADR2(VCC),
    .ADR3(VCC),
    .O(\counter_30/FROM )
  );
  X_XOR2 Madd__n0001_inst_sum_28 (
    .I0(\counter_30/CYINIT ),
    .I1(\counter_30/FROM ),
    .O(_n0001[28])
  );
  X_MUX2 Madd__n0001_inst_cy_28_59 (
    .IA(\counter_30/LOGIC_ZERO ),
    .IB(\counter_30/CYINIT ),
    .SEL(\counter_30/FROM ),
    .O(Madd__n0001_inst_cy_28)
  );
  X_ZERO \counter_30/LOGIC_ZERO_60  (
    .O(\counter_30/LOGIC_ZERO )
  );
  X_BUF \counter_28/CYINIT_61  (
    .I(Madd__n0001_inst_cy_25),
    .O(\counter_28/CYINIT )
  );
  X_INV \counter_28/SRMUX  (
    .I(reset_IBUF),
    .O(\counter_28/SRMUX_OUTPUTNOT )
  );
  X_XOR2 Madd__n0001_inst_sum_27 (
    .I0(Madd__n0001_inst_cy_26),
    .I1(\counter_28/GROM ),
    .O(_n0001[27])
  );
  X_MUX2 Madd__n0001_inst_cy_27_62 (
    .IA(\counter_28/LOGIC_ZERO ),
    .IB(Madd__n0001_inst_cy_26),
    .SEL(\counter_28/GROM ),
    .O(\counter_28/CYMUXG )
  );
  X_BUF \counter_28/COUTUSED  (
    .I(\counter_28/CYMUXG ),
    .O(Madd__n0001_inst_cy_27)
  );
  defparam \counter_28/G .INIT = 16'hF0F0;
  X_LUT4 \counter_28/G  (
    .ADR0(VCC),
    .ADR1(VCC),
    .ADR2(counter_29),
    .ADR3(VCC),
    .O(\counter_28/GROM )
  );
  defparam \counter_28/F .INIT = 16'hFF00;
  X_LUT4 \counter_28/F  (
    .ADR0(VCC),
    .ADR1(VCC),
    .ADR2(VCC),
    .ADR3(counter_28),
    .O(\counter_28/FROM )
  );
  X_XOR2 Madd__n0001_inst_sum_26 (
    .I0(\counter_28/CYINIT ),
    .I1(\counter_28/FROM ),
    .O(_n0001[26])
  );
  X_MUX2 Madd__n0001_inst_cy_26_63 (
    .IA(\counter_28/LOGIC_ZERO ),
    .IB(\counter_28/CYINIT ),
    .SEL(\counter_28/FROM ),
    .O(Madd__n0001_inst_cy_26)
  );
  X_ZERO \counter_28/LOGIC_ZERO_64  (
    .O(\counter_28/LOGIC_ZERO )
  );
  X_BUF \counter_26/CYINIT_65  (
    .I(Madd__n0001_inst_cy_23),
    .O(\counter_26/CYINIT )
  );
  X_INV \counter_26/SRMUX  (
    .I(reset_IBUF),
    .O(\counter_26/SRMUX_OUTPUTNOT )
  );
  X_XOR2 Madd__n0001_inst_sum_25 (
    .I0(Madd__n0001_inst_cy_24),
    .I1(\counter_26/GROM ),
    .O(_n0001[25])
  );
  X_MUX2 Madd__n0001_inst_cy_25_66 (
    .IA(\counter_26/LOGIC_ZERO ),
    .IB(Madd__n0001_inst_cy_24),
    .SEL(\counter_26/GROM ),
    .O(\counter_26/CYMUXG )
  );
  X_BUF \counter_26/COUTUSED  (
    .I(\counter_26/CYMUXG ),
    .O(Madd__n0001_inst_cy_25)
  );
  defparam \counter_26/G .INIT = 16'hF0F0;
  X_LUT4 \counter_26/G  (
    .ADR0(VCC),
    .ADR1(VCC),
    .ADR2(counter_27),
    .ADR3(VCC),
    .O(\counter_26/GROM )
  );
  defparam \counter_26/F .INIT = 16'hFF00;
  X_LUT4 \counter_26/F  (
    .ADR0(VCC),
    .ADR1(VCC),
    .ADR2(VCC),
    .ADR3(counter_26),
    .O(\counter_26/FROM )
  );
  X_XOR2 Madd__n0001_inst_sum_24 (
    .I0(\counter_26/CYINIT ),
    .I1(\counter_26/FROM ),
    .O(_n0001[24])
  );
  X_MUX2 Madd__n0001_inst_cy_24_67 (
    .IA(\counter_26/LOGIC_ZERO ),
    .IB(\counter_26/CYINIT ),
    .SEL(\counter_26/FROM ),
    .O(Madd__n0001_inst_cy_24)
  );
  X_ZERO \counter_26/LOGIC_ZERO_68  (
    .O(\counter_26/LOGIC_ZERO )
  );
  X_BUF \counter_25/CYINIT_69  (
    .I(Madd__n0001_inst_cy_21),
    .O(\counter_25/CYINIT )
  );
  X_INV \counter_25/SRMUX  (
    .I(reset_IBUF),
    .O(\counter_25/SRMUX_OUTPUTNOT )
  );
  X_XOR2 Madd__n0001_inst_sum_23 (
    .I0(Madd__n0001_inst_cy_22),
    .I1(\counter_25/GROM ),
    .O(_n0001[23])
  );
  X_MUX2 Madd__n0001_inst_cy_23_70 (
    .IA(\counter_25/LOGIC_ZERO ),
    .IB(Madd__n0001_inst_cy_22),
    .SEL(\counter_25/GROM ),
    .O(\counter_25/CYMUXG )
  );
  X_BUF \counter_25/XUSED  (
    .I(\counter_25/XORF ),
    .O(_n0001[22])
  );
  X_BUF \counter_25/COUTUSED  (
    .I(\counter_25/CYMUXG ),
    .O(Madd__n0001_inst_cy_23)
  );
  defparam \counter_25/G .INIT = 16'hF0F0;
  X_LUT4 \counter_25/G  (
    .ADR0(VCC),
    .ADR1(VCC),
    .ADR2(counter_25),
    .ADR3(VCC),
    .O(\counter_25/GROM )
  );
  defparam \counter_25/F .INIT = 16'hFF00;
  X_LUT4 \counter_25/F  (
    .ADR0(VCC),
    .ADR1(VCC),
    .ADR2(VCC),
    .ADR3(counter_24),
    .O(\counter_25/FROM )
  );
  X_XOR2 Madd__n0001_inst_sum_22 (
    .I0(\counter_25/CYINIT ),
    .I1(\counter_25/FROM ),
    .O(\counter_25/XORF )
  );
  X_MUX2 Madd__n0001_inst_cy_22_71 (
    .IA(\counter_25/LOGIC_ZERO ),
    .IB(\counter_25/CYINIT ),
    .SEL(\counter_25/FROM ),
    .O(Madd__n0001_inst_cy_22)
  );
  X_ZERO \counter_25/LOGIC_ZERO_72  (
    .O(\counter_25/LOGIC_ZERO )
  );
  X_BUF \counter_22/CYINIT_73  (
    .I(Madd__n0001_inst_cy_19),
    .O(\counter_22/CYINIT )
  );
  X_INV \counter_22/SRMUX  (
    .I(reset_IBUF),
    .O(\counter_22/SRMUX_OUTPUTNOT )
  );
  X_XOR2 Madd__n0001_inst_sum_21 (
    .I0(Madd__n0001_inst_cy_20),
    .I1(\counter_22/GROM ),
    .O(_n0001[21])
  );
  X_MUX2 Madd__n0001_inst_cy_21_74 (
    .IA(\counter_22/LOGIC_ZERO ),
    .IB(Madd__n0001_inst_cy_20),
    .SEL(\counter_22/GROM ),
    .O(\counter_22/CYMUXG )
  );
  X_BUF \counter_22/COUTUSED  (
    .I(\counter_22/CYMUXG ),
    .O(Madd__n0001_inst_cy_21)
  );
  defparam \counter_22/G .INIT = 16'hF0F0;
  X_LUT4 \counter_22/G  (
    .ADR0(VCC),
    .ADR1(VCC),
    .ADR2(counter_23),
    .ADR3(VCC),
    .O(\counter_22/GROM )
  );
  defparam \counter_22/F .INIT = 16'hCCCC;
  X_LUT4 \counter_22/F  (
    .ADR0(VCC),
    .ADR1(counter_22),
    .ADR2(VCC),
    .ADR3(VCC),
    .O(\counter_22/FROM )
  );
  X_XOR2 Madd__n0001_inst_sum_20 (
    .I0(\counter_22/CYINIT ),
    .I1(\counter_22/FROM ),
    .O(_n0001[20])
  );
  X_MUX2 Madd__n0001_inst_cy_20_75 (
    .IA(\counter_22/LOGIC_ZERO ),
    .IB(\counter_22/CYINIT ),
    .SEL(\counter_22/FROM ),
    .O(Madd__n0001_inst_cy_20)
  );
  X_ZERO \counter_22/LOGIC_ZERO_76  (
    .O(\counter_22/LOGIC_ZERO )
  );
  X_OR2 \counter_6/FFX/RSTOR  (
    .I0(\counter_6/SRMUX_OUTPUTNOT ),
    .I1(GSR),
    .O(\counter_6/FFX/RST )
  );
  X_FF counter_6_77 (
    .I(_n0001[4]),
    .CE(_n00021_1),
    .CLK(clk_BUFGP),
    .SET(GND),
    .RST(\counter_6/FFX/RST ),
    .O(counter_6)
  );
  X_OR2 \counter_8/FFY/RSTOR  (
    .I0(\counter_8/SRMUX_OUTPUTNOT ),
    .I1(GSR),
    .O(\counter_8/FFY/RST )
  );
  X_FF counter_9_78 (
    .I(_n0001[7]),
    .CE(_n00021_1),
    .CLK(clk_BUFGP),
    .SET(GND),
    .RST(\counter_8/FFY/RST ),
    .O(counter_9)
  );
  X_OR2 \counter_12/FFY/RSTOR  (
    .I0(\counter_12/SRMUX_OUTPUTNOT ),
    .I1(GSR),
    .O(\counter_12/FFY/RST )
  );
  X_FF counter_13_79 (
    .I(_n0001[11]),
    .CE(_n0002),
    .CLK(clk_BUFGP),
    .SET(GND),
    .RST(\counter_12/FFY/RST ),
    .O(counter_13)
  );
  X_OR2 \counter_4/FFX/RSTOR  (
    .I0(\counter_4/SRMUX_OUTPUTNOT ),
    .I1(GSR),
    .O(\counter_4/FFX/RST )
  );
  X_FF counter_4_80 (
    .I(_n0001[2]),
    .CE(_n00021_1),
    .CLK(clk_BUFGP),
    .SET(GND),
    .RST(\counter_4/FFX/RST ),
    .O(counter_4)
  );
  X_OR2 \counter_12/FFX/RSTOR  (
    .I0(\counter_12/SRMUX_OUTPUTNOT ),
    .I1(GSR),
    .O(\counter_12/FFX/RST )
  );
  X_FF counter_12_81 (
    .I(_n0001[10]),
    .CE(_n0002),
    .CLK(clk_BUFGP),
    .SET(GND),
    .RST(\counter_12/FFX/RST ),
    .O(counter_12)
  );
  X_OR2 \counter_30/FFY/RSTOR  (
    .I0(\counter_30/SRMUX_OUTPUTNOT ),
    .I1(GSR),
    .O(\counter_30/FFY/RST )
  );
  X_FF counter_31_82 (
    .I(_n0001[29]),
    .CE(_n00021_1),
    .CLK(clk_BUFGP),
    .SET(GND),
    .RST(\counter_30/FFY/RST ),
    .O(counter_31)
  );
  X_OR2 \counter_8/FFX/RSTOR  (
    .I0(\counter_8/SRMUX_OUTPUTNOT ),
    .I1(GSR),
    .O(\counter_8/FFX/RST )
  );
  X_FF counter_8_83 (
    .I(_n0001[6]),
    .CE(_n00021_1),
    .CLK(clk_BUFGP),
    .SET(GND),
    .RST(\counter_8/FFX/RST ),
    .O(counter_8)
  );
  X_OR2 \counter_11/FFY/RSTOR  (
    .I0(\counter_11/SRMUX_OUTPUTNOT ),
    .I1(GSR),
    .O(\counter_11/FFY/RST )
  );
  X_FF counter_11_84 (
    .I(_n0001[9]),
    .CE(_n0002),
    .CLK(clk_BUFGP),
    .SET(GND),
    .RST(\counter_11/FFY/RST ),
    .O(counter_11)
  );
  X_OR2 \counter_14/FFY/RSTOR  (
    .I0(\counter_14/SRMUX_OUTPUTNOT ),
    .I1(GSR),
    .O(\counter_14/FFY/RST )
  );
  X_FF counter_15_85 (
    .I(_n0001[13]),
    .CE(_n0002),
    .CLK(clk_BUFGP),
    .SET(GND),
    .RST(\counter_14/FFY/RST ),
    .O(counter_15)
  );
  X_OR2 \counter_30/FFX/RSTOR  (
    .I0(\counter_30/SRMUX_OUTPUTNOT ),
    .I1(GSR),
    .O(\counter_30/FFX/RST )
  );
  X_FF counter_30_86 (
    .I(_n0001[28]),
    .CE(_n00021_1),
    .CLK(clk_BUFGP),
    .SET(GND),
    .RST(\counter_30/FFX/RST ),
    .O(counter_30)
  );
  X_OR2 \counter_14/FFX/RSTOR  (
    .I0(\counter_14/SRMUX_OUTPUTNOT ),
    .I1(GSR),
    .O(\counter_14/FFX/RST )
  );
  X_FF counter_14_87 (
    .I(_n0001[12]),
    .CE(_n0002),
    .CLK(clk_BUFGP),
    .SET(GND),
    .RST(\counter_14/FFX/RST ),
    .O(counter_14)
  );
  X_OR2 \counter_6/FFY/RSTOR  (
    .I0(\counter_6/SRMUX_OUTPUTNOT ),
    .I1(GSR),
    .O(\counter_6/FFY/RST )
  );
  X_FF counter_7_88 (
    .I(_n0001[5]),
    .CE(_n00021_1),
    .CLK(clk_BUFGP),
    .SET(GND),
    .RST(\counter_6/FFY/RST ),
    .O(counter_7)
  );
  X_BUF \counter<5>/OMUX  (
    .I(counter_5),
    .O(\counter<5>/OD )
  );
  X_BUF \counter<5>/OUTMUX_89  (
    .I(\counter<5>/OD ),
    .O(\counter<5>/OUTMUX )
  );
  X_BUF \counter<5>/GTS_OR  (
    .I(GTS),
    .O(\counter<5>/TORGTS )
  );
  X_INV \counter<5>/ENABLEINV  (
    .I(\counter<5>/TORGTS ),
    .O(\counter<5>/ENABLE )
  );
  X_TRI counter_5_OBUF (
    .I(\counter<5>/OUTMUX ),
    .CTL(\counter<5>/ENABLE ),
    .O(counter[5])
  );
  X_OPAD \counter<5>/PAD  (
    .PAD(counter[5])
  );
  X_BUF \counter<6>/OMUX  (
    .I(counter_6),
    .O(\counter<6>/OD )
  );
  X_BUF \counter<6>/OUTMUX_90  (
    .I(\counter<6>/OD ),
    .O(\counter<6>/OUTMUX )
  );
  X_BUF \counter<6>/GTS_OR  (
    .I(GTS),
    .O(\counter<6>/TORGTS )
  );
  X_INV \counter<6>/ENABLEINV  (
    .I(\counter<6>/TORGTS ),
    .O(\counter<6>/ENABLE )
  );
  X_TRI counter_6_OBUF (
    .I(\counter<6>/OUTMUX ),
    .CTL(\counter<6>/ENABLE ),
    .O(counter[6])
  );
  X_OPAD \counter<6>/PAD  (
    .PAD(counter[6])
  );
  X_BUF \counter<7>/OMUX  (
    .I(counter_7),
    .O(\counter<7>/OD )
  );
  X_BUF \counter<7>/OUTMUX_91  (
    .I(\counter<7>/OD ),
    .O(\counter<7>/OUTMUX )
  );
  X_BUF \counter<7>/GTS_OR  (
    .I(GTS),
    .O(\counter<7>/TORGTS )
  );
  X_INV \counter<7>/ENABLEINV  (
    .I(\counter<7>/TORGTS ),
    .O(\counter<7>/ENABLE )
  );
  X_TRI counter_7_OBUF (
    .I(\counter<7>/OUTMUX ),
    .CTL(\counter<7>/ENABLE ),
    .O(counter[7])
  );
  X_OPAD \counter<7>/PAD  (
    .PAD(counter[7])
  );
  X_BUF \counter<8>/OMUX  (
    .I(counter_8),
    .O(\counter<8>/OD )
  );
  X_BUF \counter<8>/OUTMUX_92  (
    .I(\counter<8>/OD ),
    .O(\counter<8>/OUTMUX )
  );
  X_BUF \counter<8>/GTS_OR  (
    .I(GTS),
    .O(\counter<8>/TORGTS )
  );
  X_INV \counter<8>/ENABLEINV  (
    .I(\counter<8>/TORGTS ),
    .O(\counter<8>/ENABLE )
  );
  X_TRI counter_8_OBUF (
    .I(\counter<8>/OUTMUX ),
    .CTL(\counter<8>/ENABLE ),
    .O(counter[8])
  );
  X_OPAD \counter<8>/PAD  (
    .PAD(counter[8])
  );
  X_BUF \counter<9>/OMUX  (
    .I(counter_9),
    .O(\counter<9>/OD )
  );
  X_BUF \counter<9>/OUTMUX_93  (
    .I(\counter<9>/OD ),
    .O(\counter<9>/OUTMUX )
  );
  X_BUF \counter<9>/GTS_OR  (
    .I(GTS),
    .O(\counter<9>/TORGTS )
  );
  X_INV \counter<9>/ENABLEINV  (
    .I(\counter<9>/TORGTS ),
    .O(\counter<9>/ENABLE )
  );
  X_TRI counter_9_OBUF (
    .I(\counter<9>/OUTMUX ),
    .CTL(\counter<9>/ENABLE ),
    .O(counter[9])
  );
  X_OPAD \counter<9>/PAD  (
    .PAD(counter[9])
  );
  X_BUF \counter<10>/OMUX  (
    .I(counter_10),
    .O(\counter<10>/OD )
  );
  X_BUF \counter<10>/OUTMUX_94  (