prescale_counter_timesim.v

Xilinx ISE 官方源代码盘第七章 Part1

    .SEL(\counter_16/FROM ),
    .O(Madd__n0001_inst_cy_14)
  );
  X_ZERO \counter_16/LOGIC_ZERO_15  (
    .O(\counter_16/LOGIC_ZERO )
  );
  X_BUF \counter_14/CYINIT_16  (
    .I(Madd__n0001_inst_cy_11),
    .O(\counter_14/CYINIT )
  );
  X_INV \counter_14/SRMUX  (
    .I(reset_IBUF),
    .O(\counter_14/SRMUX_OUTPUTNOT )
  );
  X_XOR2 Madd__n0001_inst_sum_13 (
    .I0(Madd__n0001_inst_cy_12),
    .I1(\counter_14/GROM ),
    .O(_n0001[13])
  );
  X_MUX2 Madd__n0001_inst_cy_13_17 (
    .IA(\counter_14/LOGIC_ZERO ),
    .IB(Madd__n0001_inst_cy_12),
    .SEL(\counter_14/GROM ),
    .O(\counter_14/CYMUXG )
  );
  X_BUF \counter_14/COUTUSED  (
    .I(\counter_14/CYMUXG ),
    .O(Madd__n0001_inst_cy_13)
  );
  defparam \counter_14/G .INIT = 16'hF0F0;
  X_LUT4 \counter_14/G  (
    .ADR0(VCC),
    .ADR1(VCC),
    .ADR2(counter_15),
    .ADR3(VCC),
    .O(\counter_14/GROM )
  );
  defparam \counter_14/F .INIT = 16'hCCCC;
  X_LUT4 \counter_14/F  (
    .ADR0(VCC),
    .ADR1(counter_14),
    .ADR2(VCC),
    .ADR3(VCC),
    .O(\counter_14/FROM )
  );
  X_XOR2 Madd__n0001_inst_sum_12 (
    .I0(\counter_14/CYINIT ),
    .I1(\counter_14/FROM ),
    .O(_n0001[12])
  );
  X_MUX2 Madd__n0001_inst_cy_12_18 (
    .IA(\counter_14/LOGIC_ZERO ),
    .IB(\counter_14/CYINIT ),
    .SEL(\counter_14/FROM ),
    .O(Madd__n0001_inst_cy_12)
  );
  X_ZERO \counter_14/LOGIC_ZERO_19  (
    .O(\counter_14/LOGIC_ZERO )
  );
  X_BUF \counter_3/CYINIT_20  (
    .I(\counter_3/LOGIC_ZERO ),
    .O(\counter_3/CYINIT )
  );
  X_INV \counter_3/SRMUX  (
    .I(reset_IBUF),
    .O(\counter_3/SRMUX_OUTPUTNOT )
  );
  X_XOR2 Madd__n0001_inst_sum_1 (
    .I0(Madd__n0001_inst_cy_0),
    .I1(\counter_3/GROM ),
    .O(_n0001[1])
  );
  X_MUX2 Madd__n0001_inst_cy_1_21 (
    .IA(GLOBAL_LOGIC0),
    .IB(Madd__n0001_inst_cy_0),
    .SEL(\counter_3/GROM ),
    .O(\counter_3/CYMUXG )
  );
  X_BUF \counter_3/XUSED  (
    .I(\counter_3/FROM ),
    .O(Madd__n0001_inst_lut2_0)
  );
  X_BUF \counter_3/COUTUSED  (
    .I(\counter_3/CYMUXG ),
    .O(Madd__n0001_inst_cy_1)
  );
  defparam \counter_3/G .INIT = 16'hF0F0;
  X_LUT4 \counter_3/G  (
    .ADR0(GLOBAL_LOGIC0),
    .ADR1(VCC),
    .ADR2(counter_3),
    .ADR3(VCC),
    .O(\counter_3/GROM )
  );
  defparam Madd__n0001_inst_lut2_01.INIT = 16'h3333;
  X_LUT4 Madd__n0001_inst_lut2_01 (
    .ADR0(GLOBAL_LOGIC1),
    .ADR1(counter_2),
    .ADR2(VCC),
    .ADR3(VCC),
    .O(\counter_3/FROM )
  );
  X_MUX2 Madd__n0001_inst_cy_0_22 (
    .IA(GLOBAL_LOGIC1),
    .IB(\counter_3/CYINIT ),
    .SEL(\counter_3/FROM ),
    .O(Madd__n0001_inst_cy_0)
  );
  X_ZERO \counter_3/LOGIC_ZERO_23  (
    .O(\counter_3/LOGIC_ZERO )
  );
  X_BUF \counter_12/CYINIT_24  (
    .I(Madd__n0001_inst_cy_9),
    .O(\counter_12/CYINIT )
  );
  X_INV \counter_12/SRMUX  (
    .I(reset_IBUF),
    .O(\counter_12/SRMUX_OUTPUTNOT )
  );
  X_XOR2 Madd__n0001_inst_sum_11 (
    .I0(Madd__n0001_inst_cy_10),
    .I1(\counter_12/GROM ),
    .O(_n0001[11])
  );
  X_MUX2 Madd__n0001_inst_cy_11_25 (
    .IA(\counter_12/LOGIC_ZERO ),
    .IB(Madd__n0001_inst_cy_10),
    .SEL(\counter_12/GROM ),
    .O(\counter_12/CYMUXG )
  );
  X_BUF \counter_12/COUTUSED  (
    .I(\counter_12/CYMUXG ),
    .O(Madd__n0001_inst_cy_11)
  );
  defparam \counter_12/G .INIT = 16'hF0F0;
  X_LUT4 \counter_12/G  (
    .ADR0(VCC),
    .ADR1(VCC),
    .ADR2(counter_13),
    .ADR3(VCC),
    .O(\counter_12/GROM )
  );
  defparam \counter_12/F .INIT = 16'hCCCC;
  X_LUT4 \counter_12/F  (
    .ADR0(VCC),
    .ADR1(counter_12),
    .ADR2(VCC),
    .ADR3(VCC),
    .O(\counter_12/FROM )
  );
  X_XOR2 Madd__n0001_inst_sum_10 (
    .I0(\counter_12/CYINIT ),
    .I1(\counter_12/FROM ),
    .O(_n0001[10])
  );
  X_MUX2 Madd__n0001_inst_cy_10_26 (
    .IA(\counter_12/LOGIC_ZERO ),
    .IB(\counter_12/CYINIT ),
    .SEL(\counter_12/FROM ),
    .O(Madd__n0001_inst_cy_10)
  );
  X_ZERO \counter_12/LOGIC_ZERO_27  (
    .O(\counter_12/LOGIC_ZERO )
  );
  X_BUF \counter_11/CYINIT_28  (
    .I(Madd__n0001_inst_cy_7),
    .O(\counter_11/CYINIT )
  );
  X_INV \counter_11/SRMUX  (
    .I(reset_IBUF),
    .O(\counter_11/SRMUX_OUTPUTNOT )
  );
  X_XOR2 Madd__n0001_inst_sum_9 (
    .I0(Madd__n0001_inst_cy_8),
    .I1(\counter_11/GROM ),
    .O(_n0001[9])
  );
  X_MUX2 Madd__n0001_inst_cy_9_29 (
    .IA(\counter_11/LOGIC_ZERO ),
    .IB(Madd__n0001_inst_cy_8),
    .SEL(\counter_11/GROM ),
    .O(\counter_11/CYMUXG )
  );
  X_BUF \counter_11/XUSED  (
    .I(\counter_11/XORF ),
    .O(_n0001[8])
  );
  X_BUF \counter_11/COUTUSED  (
    .I(\counter_11/CYMUXG ),
    .O(Madd__n0001_inst_cy_9)
  );
  defparam \counter_11/G .INIT = 16'hF0F0;
  X_LUT4 \counter_11/G  (
    .ADR0(VCC),
    .ADR1(VCC),
    .ADR2(counter_11),
    .ADR3(VCC),
    .O(\counter_11/GROM )
  );
  defparam \counter_11/F .INIT = 16'hFF00;
  X_LUT4 \counter_11/F  (
    .ADR0(VCC),
    .ADR1(VCC),
    .ADR2(VCC),
    .ADR3(counter_10),
    .O(\counter_11/FROM )
  );
  X_XOR2 Madd__n0001_inst_sum_8 (
    .I0(\counter_11/CYINIT ),
    .I1(\counter_11/FROM ),
    .O(\counter_11/XORF )
  );
  X_MUX2 Madd__n0001_inst_cy_8_30 (
    .IA(\counter_11/LOGIC_ZERO ),
    .IB(\counter_11/CYINIT ),
    .SEL(\counter_11/FROM ),
    .O(Madd__n0001_inst_cy_8)
  );
  X_ZERO \counter_11/LOGIC_ZERO_31  (
    .O(\counter_11/LOGIC_ZERO )
  );
  X_BUF \counter_8/CYINIT_32  (
    .I(Madd__n0001_inst_cy_5),
    .O(\counter_8/CYINIT )
  );
  X_INV \counter_8/SRMUX  (
    .I(reset_IBUF),
    .O(\counter_8/SRMUX_OUTPUTNOT )
  );
  X_XOR2 Madd__n0001_inst_sum_7 (
    .I0(Madd__n0001_inst_cy_6),
    .I1(\counter_8/GROM ),
    .O(_n0001[7])
  );
  X_MUX2 Madd__n0001_inst_cy_7_33 (
    .IA(\counter_8/LOGIC_ZERO ),
    .IB(Madd__n0001_inst_cy_6),
    .SEL(\counter_8/GROM ),
    .O(\counter_8/CYMUXG )
  );
  X_BUF \counter_8/COUTUSED  (
    .I(\counter_8/CYMUXG ),
    .O(Madd__n0001_inst_cy_7)
  );
  defparam \counter_8/G .INIT = 16'hF0F0;
  X_LUT4 \counter_8/G  (
    .ADR0(VCC),
    .ADR1(VCC),
    .ADR2(counter_9),
    .ADR3(VCC),
    .O(\counter_8/GROM )
  );
  defparam \counter_8/F .INIT = 16'hCCCC;
  X_LUT4 \counter_8/F  (
    .ADR0(VCC),
    .ADR1(counter_8),
    .ADR2(VCC),
    .ADR3(VCC),
    .O(\counter_8/FROM )
  );
  X_XOR2 Madd__n0001_inst_sum_6 (
    .I0(\counter_8/CYINIT ),
    .I1(\counter_8/FROM ),
    .O(_n0001[6])
  );
  X_MUX2 Madd__n0001_inst_cy_6_34 (
    .IA(\counter_8/LOGIC_ZERO ),
    .IB(\counter_8/CYINIT ),
    .SEL(\counter_8/FROM ),
    .O(Madd__n0001_inst_cy_6)
  );
  X_ZERO \counter_8/LOGIC_ZERO_35  (
    .O(\counter_8/LOGIC_ZERO )
  );
  X_BUF \counter_6/CYINIT_36  (
    .I(Madd__n0001_inst_cy_3),
    .O(\counter_6/CYINIT )
  );
  X_INV \counter_6/SRMUX  (
    .I(reset_IBUF),
    .O(\counter_6/SRMUX_OUTPUTNOT )
  );
  X_XOR2 Madd__n0001_inst_sum_5 (
    .I0(Madd__n0001_inst_cy_4),
    .I1(\counter_6/GROM ),
    .O(_n0001[5])
  );
  X_MUX2 Madd__n0001_inst_cy_5_37 (
    .IA(\counter_6/LOGIC_ZERO ),
    .IB(Madd__n0001_inst_cy_4),
    .SEL(\counter_6/GROM ),
    .O(\counter_6/CYMUXG )
  );
  X_BUF \counter_6/COUTUSED  (
    .I(\counter_6/CYMUXG ),
    .O(Madd__n0001_inst_cy_5)
  );
  defparam \counter_6/G .INIT = 16'hFF00;
  X_LUT4 \counter_6/G  (
    .ADR0(VCC),
    .ADR1(VCC),
    .ADR2(VCC),
    .ADR3(counter_7),
    .O(\counter_6/GROM )
  );
  defparam \counter_6/F .INIT = 16'hCCCC;
  X_LUT4 \counter_6/F  (
    .ADR0(VCC),
    .ADR1(counter_6),
    .ADR2(VCC),
    .ADR3(VCC),
    .O(\counter_6/FROM )
  );
  X_XOR2 Madd__n0001_inst_sum_4 (
    .I0(\counter_6/CYINIT ),
    .I1(\counter_6/FROM ),
    .O(_n0001[4])
  );
  X_MUX2 Madd__n0001_inst_cy_4_38 (
    .IA(\counter_6/LOGIC_ZERO ),
    .IB(\counter_6/CYINIT ),
    .SEL(\counter_6/FROM ),
    .O(Madd__n0001_inst_cy_4)
  );
  X_ZERO \counter_6/LOGIC_ZERO_39  (
    .O(\counter_6/LOGIC_ZERO )
  );
  X_BUF \counter_4/CYINIT_40  (
    .I(Madd__n0001_inst_cy_1),
    .O(\counter_4/CYINIT )
  );
  X_INV \counter_4/SRMUX  (
    .I(reset_IBUF),
    .O(\counter_4/SRMUX_OUTPUTNOT )
  );
  X_XOR2 Madd__n0001_inst_sum_3 (
    .I0(Madd__n0001_inst_cy_2),
    .I1(\counter_4/GROM ),
    .O(_n0001[3])
  );
  X_MUX2 Madd__n0001_inst_cy_3_41 (
    .IA(\counter_4/LOGIC_ZERO ),
    .IB(Madd__n0001_inst_cy_2),
    .SEL(\counter_4/GROM ),
    .O(\counter_4/CYMUXG )
  );
  X_BUF \counter_4/COUTUSED  (
    .I(\counter_4/CYMUXG ),
    .O(Madd__n0001_inst_cy_3)
  );
  defparam \counter_4/G .INIT = 16'hF0F0;
  X_LUT4 \counter_4/G  (
    .ADR0(VCC),
    .ADR1(VCC),
    .ADR2(counter_5),
    .ADR3(VCC),
    .O(\counter_4/GROM )
  );
  defparam \counter_4/F .INIT = 16'hCCCC;
  X_LUT4 \counter_4/F  (
    .ADR0(VCC),
    .ADR1(counter_4),
    .ADR2(VCC),
    .ADR3(VCC),
    .O(\counter_4/FROM )
  );
  X_XOR2 Madd__n0001_inst_sum_2 (
    .I0(\counter_4/CYINIT ),
    .I1(\counter_4/FROM ),
    .O(_n0001[2])
  );
  X_MUX2 Madd__n0001_inst_cy_2_42 (
    .IA(\counter_4/LOGIC_ZERO ),
    .IB(\counter_4/CYINIT ),
    .SEL(\counter_4/FROM ),
    .O(Madd__n0001_inst_cy_2)
  );
  X_ZERO \counter_4/LOGIC_ZERO_43  (
    .O(\counter_4/LOGIC_ZERO )
  );
  X_OR2 \counter_4/FFY/RSTOR  (
    .I0(\counter_4/SRMUX_OUTPUTNOT ),
    .I1(GSR),
    .O(\counter_4/FFY/RST )
  );
  X_FF counter_5_44 (
    .I(_n0001[3]),
    .CE(_n00021_1),
    .CLK(clk_BUFGP),
    .SET(GND),
    .RST(\counter_4/FFY/RST ),
    .O(counter_5)
  );
  X_BUF \counter<4>/OMUX  (
    .I(counter_4),
    .O(\counter<4>/OD )
  );
  X_BUF \counter<4>/OUTMUX_45  (
    .I(\counter<4>/OD ),
    .O(\counter<4>/OUTMUX )
  );
  X_BUF \counter<4>/GTS_OR  (
    .I(GTS),
    .O(\counter<4>/TORGTS )
  );
  X_INV \counter<4>/ENABLEINV  (
    .I(\counter<4>/TORGTS ),
    .O(\counter<4>/ENABLE )
  );
  X_TRI counter_4_OBUF (
    .I(\counter<4>/OUTMUX ),
    .CTL(\counter<4>/ENABLE ),
    .O(counter[4])
  );
  X_OPAD \counter<4>/PAD  (
    .PAD(counter[4])
  );
  X_BUF \counter<3>/OMUX  (
    .I(counter_3),
    .O(\counter<3>/OD )
  );
  X_BUF \counter<3>/OUTMUX_46  (
    .I(\counter<3>/OD ),
    .O(\counter<3>/OUTMUX )
  );
  X_BUF \counter<3>/GTS_OR  (
    .I(GTS),
    .O(\counter<3>/TORGTS )
  );
  X_INV \counter<3>/ENABLEINV  (
    .I(\counter<3>/TORGTS ),
    .O(\counter<3>/ENABLE )
  );
  X_TRI counter_3_OBUF (
    .I(\counter<3>/OUTMUX ),
    .CTL(\counter<3>/ENABLE ),
    .O(counter[3])
  );
  X_OPAD \counter<3>/PAD  (
    .PAD(counter[3])
  );
  X_BUF \counter<2>/OMUX  (
    .I(counter_2),
    .O(\counter<2>/OD )
  );
  X_BUF \counter<2>/OUTMUX_47  (
    .I(\counter<2>/OD ),
    .O(\counter<2>/OUTMUX )
  );
  X_BUF \counter<2>/GTS_OR  (
    .I(GTS),
    .O(\counter<2>/TORGTS )
  );
  X_INV \counter<2>/ENABLEINV  (
    .I(\counter<2>/TORGTS ),
    .O(\counter<2>/ENABLE )
  );
  X_TRI counter_2_OBUF (
    .I(\counter<2>/OUTMUX ),
    .CTL(\counter<2>/ENABLE ),
    .O(counter[2])
  );
  X_OPAD \counter<2>/PAD  (
    .PAD(counter[2])
  );
  X_BUF \counter<1>/OMUX  (
    .I(counter_1),
    .O(\counter<1>/OD )
  );
  X_BUF \counter<1>/OUTMUX_48  (
    .I(\counter<1>/OD ),
    .O(\counter<1>/OUTMUX )
  );
  X_BUF \counter<1>/GTS_OR  (
    .I(GTS),
    .O(\counter<1>/TORGTS )
  );
  X_INV \counter<1>/ENABLEINV  (
    .I(\counter<1>/TORGTS ),
    .O(\counter<1>/ENABLE )
  );
  X_TRI counter_1_OBUF (
    .I(\counter<1>/OUTMUX ),
    .CTL(\counter<1>/ENABLE ),
    .O(counter[1])
  );
  X_OPAD \counter<1>/PAD  (
    .PAD(counter[1])
  );
  X_BUF \counter<29>/OMUX  (
    .I(counter_29),
    .O(\counter<29>/OD )
  );
  X_BUF \counter<29>/OUTMUX_49  (
    .I(\counter<29>/OD ),
    .O(\counter<29>/OUTMUX )
  );
  X_BUF \counter<29>/GTS_OR  (
    .I(GTS),
    .O(\counter<29>/TORGTS )
  );
  X_INV \counter<29>/ENABLEINV  (
    .I(\counter<29>/TORGTS ),
    .O(\counter<29>/ENABLE )
  );
  X_TRI counter_29_OBUF (
    .I(\counter<29>/OUTMUX ),
    .CTL(\counter<29>/ENABLE ),
    .O(counter[29])
  );
  X_OPAD \counter<29>/PAD  (
    .PAD(counter[29])
  );
  X_BUF \counter<0>/OMUX  (
    .I(counter_0),
    .O(\counter<0>/OD )
  );
  X_BUF \counter<0>/OUTMUX_50  (
    .I(\counter<0>/OD ),
    .O(\counter<0>/OUTMUX )
  );
  X_BUF \counter<0>/GTS_OR  (
    .I(GTS),
    .O(\counter<0>/TORGTS )
  );
  X_INV \counter<0>/ENABLEINV  (
    .I(\counter<0>/TORGTS ),
    .O(\counter<0>/ENABLE )
  );
  X_TRI counter_0_OBUF (
    .I(\counter<0>/OUTMUX ),
    .CTL(\counter<0>/ENABLE ),
    .O(counter[0])
  );
  X_OPAD \counter<0>/PAD  (
    .PAD(counter[0])
  );
  X_BUF reset_IBUF_51 (
    .I(reset),
    .O(\reset/IBUF )
  );
  X_BUF \reset/IMUX  (
    .I(\reset/IBUF ),
    .O(reset_IBUF)
  );
  X_IPAD \reset/PAD  (
    .PAD(reset)
  );
  X_BUF \counter<28>/OMUX  (
    .I(counter_28),
    .O(\counter<28>/OD )
  );
  X_BUF \counter<28>/OUTMUX_52  (
    .I(\counter<28>/OD ),
    .O(\counter<28>/OUTMUX )
  );
  X_BUF \counter<28>/GTS_OR  (
    .I(GTS),
    .O(\counter<28>/TORGTS )
  );
  X_INV \counter<28>/ENABLEINV  (
    .I(\counter<28>/TORGTS ),
    .O(\counter<28>/ENABLE )
  );
  X_TRI counter_28_OBUF (
    .I(\counter<28>/OUTMUX ),
    .CTL(\counter<28>/ENABLE ),
    .O(counter[28])
  );
  X_OPAD \counter<28>/PAD  (
    .PAD(counter[28])
  );
  X_BUF \counter<27>/OMUX  (
    .I(counter_27),
    .O(\counter<27>/OD )
  );
  X_BUF \counter<27>/OUTMUX_53  (
    .I(\counter<27>/OD ),
    .O(\counter<27>/OUTMUX )
  );
  X_BUF \counter<27>/GTS_OR  (
    .I(GTS),
    .O(\counter<27>/TORGTS )
  );
  X_INV \counter<27>/ENABLEINV  (
    .I(\counter<27>/TORGTS ),
    .O(\counter<27>/ENABLE )
  );
  X_TRI counter_27_OBUF (
    .I(\counter<27>/OUTMUX ),
    .CTL(\counter<27>/ENABLE ),
    .O(counter[27])
  );
  X_OPAD \counter<27>/PAD  (
    .PAD(counter[27])
  );
  X_OR2 \counter_3/FFY/RSTOR  (
    .I0(\counter_3/SRMUX_OUTPUTNOT ),
    .I1(GSR),
    .O(\counter_3/FFY/RST )
  );
  X_FF counter_3_54 (
    .I(_n0001[1]),
    .CE(_n00021_1),
    .CLK(clk_BUFGP),
    .SET(GND),
    .RST(\counter_3/FFY/RST ),
    .O(counter_3)
  );
  X_INV \counter_0/SRMUX  (
    .I(reset_IBUF),