prescale_counter_timesim.v

Xilinx ISE 官方源代码盘第七章 Part1

// Xilinx Verilog produced by program ngd2ver F.23
// Command: -quiet -w -log __projnav/ngd2ver.log prescale_counter.nga prescale_counter_timesim.v 
// Input file: prescale_counter.nga
// Output file: prescale_counter_timesim.v
// Design name: prescale_counter
// Xilinx: C:/Xilinx
// # of Entities: 1
// Device: v100ebg352-6 (PRODUCTION 1.68 2002-06-19)

// The output of ngd2ver is a simulation model. This netlist uses simulation
// primitives which may not represent the true implementation of the device,
// however the netlist is functionally correct and should not be modified.
// This file cannot be synthesized and should only be used with supported
// simulation, static timing analysis and formal verification software tools.
// Please refer to the documentation on using third party static timing analysis
// and formal verification software to use the netlist for that purpose.

`timescale 1 ns/1 ps

module prescale_counter (
  reset, clk, counter
);
  input reset;
  input clk;
  output [31 : 0] counter;
  wire counter_5;
  wire counter_6;
  wire counter_7;
  wire counter_8;
  wire counter_9;
  wire \clk_BUFGP/IBUFG ;
  wire counter_10;
  wire counter_11;
  wire counter_12;
  wire counter_20;
  wire counter_13;
  wire counter_21;
  wire counter_14;
  wire counter_22;
  wire counter_30;
  wire counter_15;
  wire counter_23;
  wire counter_31;
  wire counter_16;
  wire counter_24;
  wire counter_17;
  wire counter_25;
  wire counter_18;
  wire counter_26;
  wire counter_19;
  wire counter_27;
  wire counter_28;
  wire counter_29;
  wire reset_IBUF;
  wire counter_0;
  wire counter_1;
  wire counter_2;
  wire counter_3;
  wire counter_4;
  wire clk_BUFGP;
  wire _n00021_1;
  wire Madd__n0001_inst_cy_1;
  wire GLOBAL_LOGIC1;
  wire GLOBAL_LOGIC0;
  wire Madd__n0001_inst_lut2_0;
  wire Madd__n0001_inst_cy_3;
  wire Madd__n0001_inst_cy_5;
  wire Madd__n0001_inst_cy_7;
  wire _n0002;
  wire Madd__n0001_inst_cy_9;
  wire Madd__n0001_inst_cy_11;
  wire Madd__n0001_inst_cy_13;
  wire Madd__n0001_inst_cy_15;
  wire Madd__n0001_inst_cy_17;
  wire Madd__n0001_inst_cy_19;
  wire Madd__n0001_inst_cy_21;
  wire Madd__n0001_inst_cy_23;
  wire Madd__n0001_inst_cy_25;
  wire Madd__n0001_inst_cy_27;
  wire GSR = glbl.GSR;
  wire GTS = glbl.GTS;
  wire \counter<18>/OD ;
  wire \counter<18>/OUTMUX ;
  wire \counter<18>/TORGTS ;
  wire \counter<18>/ENABLE ;
  wire \counter<26>/OD ;
  wire \counter<26>/OUTMUX ;
  wire \counter<26>/TORGTS ;
  wire \counter<26>/ENABLE ;
  wire \counter<25>/OD ;
  wire \counter<25>/OUTMUX ;
  wire \counter<25>/TORGTS ;
  wire \counter<25>/ENABLE ;
  wire \counter<19>/OD ;
  wire \counter<19>/OUTMUX ;
  wire \counter<19>/TORGTS ;
  wire \counter<19>/ENABLE ;
  wire \counter_20/SRMUX_OUTPUTNOT ;
  wire \counter_20/CYINIT ;
  wire Madd__n0001_inst_cy_18;
  wire \counter_20/GROM ;
  wire \counter_20/LOGIC_ZERO ;
  wire \counter_20/CYMUXG ;
  wire \counter_20/FROM ;
  wire \counter_18/SRMUX_OUTPUTNOT ;
  wire \counter_18/CYINIT ;
  wire Madd__n0001_inst_cy_16;
  wire \counter_18/GROM ;
  wire \counter_18/LOGIC_ZERO ;
  wire \counter_18/CYMUXG ;
  wire \counter_18/FROM ;
  wire \counter_16/SRMUX_OUTPUTNOT ;
  wire \counter_16/CYINIT ;
  wire Madd__n0001_inst_cy_14;
  wire \counter_16/GROM ;
  wire \counter_16/LOGIC_ZERO ;
  wire \counter_16/CYMUXG ;
  wire \counter_16/FROM ;
  wire \counter_14/SRMUX_OUTPUTNOT ;
  wire \counter_14/CYINIT ;
  wire Madd__n0001_inst_cy_12;
  wire \counter_14/GROM ;
  wire \counter_14/LOGIC_ZERO ;
  wire \counter_14/CYMUXG ;
  wire \counter_14/FROM ;
  wire \counter_3/SRMUX_OUTPUTNOT ;
  wire \counter_3/LOGIC_ZERO ;
  wire \counter_3/CYINIT ;
  wire Madd__n0001_inst_cy_0;
  wire \counter_3/GROM ;
  wire \counter_3/CYMUXG ;
  wire \counter_3/FROM ;
  wire \counter_12/SRMUX_OUTPUTNOT ;
  wire \counter_12/CYINIT ;
  wire Madd__n0001_inst_cy_10;
  wire \counter_12/GROM ;
  wire \counter_12/LOGIC_ZERO ;
  wire \counter_12/CYMUXG ;
  wire \counter_12/FROM ;
  wire \counter_11/SRMUX_OUTPUTNOT ;
  wire \counter_11/CYINIT ;
  wire Madd__n0001_inst_cy_8;
  wire \counter_11/GROM ;
  wire \counter_11/LOGIC_ZERO ;
  wire \counter_11/CYMUXG ;
  wire \counter_11/XORF ;
  wire \counter_11/FROM ;
  wire \counter_8/SRMUX_OUTPUTNOT ;
  wire \counter_8/CYINIT ;
  wire Madd__n0001_inst_cy_6;
  wire \counter_8/GROM ;
  wire \counter_8/LOGIC_ZERO ;
  wire \counter_8/CYMUXG ;
  wire \counter_8/FROM ;
  wire \counter_6/SRMUX_OUTPUTNOT ;
  wire \counter_6/CYINIT ;
  wire Madd__n0001_inst_cy_4;
  wire \counter_6/GROM ;
  wire \counter_6/LOGIC_ZERO ;
  wire \counter_6/CYMUXG ;
  wire \counter_6/FROM ;
  wire \counter_4/SRMUX_OUTPUTNOT ;
  wire \counter_4/CYINIT ;
  wire Madd__n0001_inst_cy_2;
  wire \counter_4/GROM ;
  wire \counter_4/LOGIC_ZERO ;
  wire \counter_4/CYMUXG ;
  wire \counter_4/FROM ;
  wire \counter_4/FFY/RST ;
  wire \counter<4>/OD ;
  wire \counter<4>/OUTMUX ;
  wire \counter<4>/TORGTS ;
  wire \counter<4>/ENABLE ;
  wire \counter<3>/OD ;
  wire \counter<3>/OUTMUX ;
  wire \counter<3>/TORGTS ;
  wire \counter<3>/ENABLE ;
  wire \counter<2>/OD ;
  wire \counter<2>/OUTMUX ;
  wire \counter<2>/TORGTS ;
  wire \counter<2>/ENABLE ;
  wire \counter<1>/OD ;
  wire \counter<1>/OUTMUX ;
  wire \counter<1>/TORGTS ;
  wire \counter<1>/ENABLE ;
  wire \counter<29>/OD ;
  wire \counter<29>/OUTMUX ;
  wire \counter<29>/TORGTS ;
  wire \counter<29>/ENABLE ;
  wire \counter<0>/OD ;
  wire \counter<0>/OUTMUX ;
  wire \counter<0>/TORGTS ;
  wire \counter<0>/ENABLE ;
  wire \reset/IBUF ;
  wire \counter<28>/OD ;
  wire \counter<28>/OUTMUX ;
  wire \counter<28>/TORGTS ;
  wire \counter<28>/ENABLE ;
  wire \counter<27>/OD ;
  wire \counter<27>/OUTMUX ;
  wire \counter<27>/TORGTS ;
  wire \counter<27>/ENABLE ;
  wire \counter_3/FFY/RST ;
  wire \counter_0/SRMUX_OUTPUTNOT ;
  wire \counter_0/BXMUXNOT ;
  wire \counter_24/SRMUX_OUTPUTNOT ;
  wire \counter_24/GROM ;
  wire \counter_24/FFY/RST ;
  wire \counter_2/SRMUX_OUTPUTNOT ;
  wire \counter_2/GROM ;
  wire \counter_2/FROM ;
  wire \counter_30/SRMUX_OUTPUTNOT ;
  wire \counter_30/CYINIT ;
  wire Madd__n0001_inst_cy_28;
  wire counter_31_rt;
  wire \counter_30/FROM ;
  wire \counter_30/LOGIC_ZERO ;
  wire \counter_28/SRMUX_OUTPUTNOT ;
  wire \counter_28/CYINIT ;
  wire Madd__n0001_inst_cy_26;
  wire \counter_28/GROM ;
  wire \counter_28/LOGIC_ZERO ;
  wire \counter_28/CYMUXG ;
  wire \counter_28/FROM ;
  wire \counter_26/SRMUX_OUTPUTNOT ;
  wire \counter_26/CYINIT ;
  wire Madd__n0001_inst_cy_24;
  wire \counter_26/GROM ;
  wire \counter_26/LOGIC_ZERO ;
  wire \counter_26/CYMUXG ;
  wire \counter_26/FROM ;
  wire \counter_25/SRMUX_OUTPUTNOT ;
  wire \counter_25/CYINIT ;
  wire Madd__n0001_inst_cy_22;
  wire \counter_25/GROM ;
  wire \counter_25/LOGIC_ZERO ;
  wire \counter_25/CYMUXG ;
  wire \counter_25/XORF ;
  wire \counter_25/FROM ;
  wire \counter_22/SRMUX_OUTPUTNOT ;
  wire \counter_22/CYINIT ;
  wire Madd__n0001_inst_cy_20;
  wire \counter_22/GROM ;
  wire \counter_22/LOGIC_ZERO ;
  wire \counter_22/CYMUXG ;
  wire \counter_22/FROM ;
  wire \counter_6/FFX/RST ;
  wire \counter_8/FFY/RST ;
  wire \counter_12/FFY/RST ;
  wire \counter_4/FFX/RST ;
  wire \counter_12/FFX/RST ;
  wire \counter_30/FFY/RST ;
  wire \counter_8/FFX/RST ;
  wire \counter_11/FFY/RST ;
  wire \counter_14/FFY/RST ;
  wire \counter_30/FFX/RST ;
  wire \counter_14/FFX/RST ;
  wire \counter_6/FFY/RST ;
  wire \counter<5>/OD ;
  wire \counter<5>/OUTMUX ;
  wire \counter<5>/TORGTS ;
  wire \counter<5>/ENABLE ;
  wire \counter<6>/OD ;
  wire \counter<6>/OUTMUX ;
  wire \counter<6>/TORGTS ;
  wire \counter<6>/ENABLE ;
  wire \counter<7>/OD ;
  wire \counter<7>/OUTMUX ;
  wire \counter<7>/TORGTS ;
  wire \counter<7>/ENABLE ;
  wire \counter<8>/OD ;
  wire \counter<8>/OUTMUX ;
  wire \counter<8>/TORGTS ;
  wire \counter<8>/ENABLE ;
  wire \counter<9>/OD ;
  wire \counter<9>/OUTMUX ;
  wire \counter<9>/TORGTS ;
  wire \counter<9>/ENABLE ;
  wire \counter<10>/OD ;
  wire \counter<10>/OUTMUX ;
  wire \counter<10>/TORGTS ;
  wire \counter<10>/ENABLE ;
  wire \counter<11>/OD ;
  wire \counter<11>/OUTMUX ;
  wire \counter<11>/TORGTS ;
  wire \counter<11>/ENABLE ;
  wire \counter<12>/OD ;
  wire \counter<12>/OUTMUX ;
  wire \counter<12>/TORGTS ;
  wire \counter<12>/ENABLE ;
  wire \counter<20>/OD ;
  wire \counter<20>/OUTMUX ;
  wire \counter<20>/TORGTS ;
  wire \counter<20>/ENABLE ;
  wire \counter<13>/OD ;
  wire \counter<13>/OUTMUX ;
  wire \counter<13>/TORGTS ;
  wire \counter<13>/ENABLE ;
  wire \counter<21>/OD ;
  wire \counter<21>/OUTMUX ;
  wire \counter<21>/TORGTS ;
  wire \counter<21>/ENABLE ;
  wire \counter<14>/OD ;
  wire \counter<14>/OUTMUX ;
  wire \counter<14>/TORGTS ;
  wire \counter<14>/ENABLE ;
  wire \counter<22>/OD ;
  wire \counter<22>/OUTMUX ;
  wire \counter<22>/TORGTS ;
  wire \counter<22>/ENABLE ;
  wire \counter<30>/OD ;
  wire \counter<30>/OUTMUX ;
  wire \counter<30>/TORGTS ;
  wire \counter<30>/ENABLE ;
  wire \counter<15>/OD ;
  wire \counter<15>/OUTMUX ;
  wire \counter<15>/TORGTS ;
  wire \counter<15>/ENABLE ;
  wire \counter<23>/OD ;
  wire \counter<23>/OUTMUX ;
  wire \counter<23>/TORGTS ;
  wire \counter<23>/ENABLE ;
  wire \counter<31>/OD ;
  wire \counter<31>/OUTMUX ;
  wire \counter<31>/TORGTS ;
  wire \counter<31>/ENABLE ;
  wire \counter<16>/OD ;
  wire \counter<16>/OUTMUX ;
  wire \counter<16>/TORGTS ;
  wire \counter<16>/ENABLE ;
  wire \counter<24>/OD ;
  wire \counter<24>/OUTMUX ;
  wire \counter<24>/TORGTS ;
  wire \counter<24>/ENABLE ;
  wire \counter<17>/OD ;
  wire \counter<17>/OUTMUX ;
  wire \counter<17>/TORGTS ;
  wire \counter<17>/ENABLE ;
  wire \counter_2/FFX/RST ;
  wire \counter_18/FFY/RST ;
  wire \counter_20/FFY/RST ;
  wire \counter_26/FFY/RST ;
  wire \counter_22/FFY/RST ;
  wire \counter_25/FFY/RST ;
  wire \counter_16/FFY/RST ;
  wire \counter_16/FFX/RST ;
  wire \counter_28/FFY/RST ;
  wire \counter_18/FFX/RST ;
  wire \counter_20/FFX/RST ;
  wire \counter_22/FFX/RST ;
  wire \counter_2/FFY/RST ;
  wire \counter_26/FFX/RST ;
  wire \counter_28/FFX/RST ;
  wire \counter_0/FFY/RST ;
  wire \counter_0/FFX/RST ;
  wire \clk_BUFGP/BUFG/CE ;
  wire \PWR_VCC_0/FROM ;
  wire VCC;
  wire GND;
  wire [29 : 1] _n0001;
  wire [1 : 1] _n0000;
  initial $sdf_annotate("prescale_counter_timesim.sdf");
  X_BUF \counter<18>/OMUX  (
    .I(counter_18),
    .O(\counter<18>/OD )
  );
  X_BUF \counter<18>/OUTMUX_0  (
    .I(\counter<18>/OD ),
    .O(\counter<18>/OUTMUX )
  );
  X_BUF \counter<18>/GTS_OR  (
    .I(GTS),
    .O(\counter<18>/TORGTS )
  );
  X_INV \counter<18>/ENABLEINV  (
    .I(\counter<18>/TORGTS ),
    .O(\counter<18>/ENABLE )
  );
  X_TRI counter_18_OBUF (
    .I(\counter<18>/OUTMUX ),
    .CTL(\counter<18>/ENABLE ),
    .O(counter[18])
  );
  X_OPAD \counter<18>/PAD  (
    .PAD(counter[18])
  );
  X_BUF \counter<26>/OMUX  (
    .I(counter_26),
    .O(\counter<26>/OD )
  );
  X_BUF \counter<26>/OUTMUX_1  (
    .I(\counter<26>/OD ),
    .O(\counter<26>/OUTMUX )
  );
  X_BUF \counter<26>/GTS_OR  (
    .I(GTS),
    .O(\counter<26>/TORGTS )
  );
  X_INV \counter<26>/ENABLEINV  (
    .I(\counter<26>/TORGTS ),
    .O(\counter<26>/ENABLE )
  );
  X_TRI counter_26_OBUF (
    .I(\counter<26>/OUTMUX ),
    .CTL(\counter<26>/ENABLE ),
    .O(counter[26])
  );
  X_OPAD \counter<26>/PAD  (
    .PAD(counter[26])
  );
  X_BUF \counter<25>/OMUX  (
    .I(counter_25),
    .O(\counter<25>/OD )
  );
  X_BUF \counter<25>/OUTMUX_2  (
    .I(\counter<25>/OD ),
    .O(\counter<25>/OUTMUX )
  );
  X_BUF \counter<25>/GTS_OR  (
    .I(GTS),
    .O(\counter<25>/TORGTS )
  );
  X_INV \counter<25>/ENABLEINV  (
    .I(\counter<25>/TORGTS ),
    .O(\counter<25>/ENABLE )
  );
  X_TRI counter_25_OBUF (
    .I(\counter<25>/OUTMUX ),
    .CTL(\counter<25>/ENABLE ),
    .O(counter[25])
  );
  X_OPAD \counter<25>/PAD  (
    .PAD(counter[25])
  );
  X_BUF \counter<19>/OMUX  (
    .I(counter_19),
    .O(\counter<19>/OD )
  );
  X_BUF \counter<19>/OUTMUX_3  (
    .I(\counter<19>/OD ),
    .O(\counter<19>/OUTMUX )
  );
  X_BUF \counter<19>/GTS_OR  (
    .I(GTS),
    .O(\counter<19>/TORGTS )
  );
  X_INV \counter<19>/ENABLEINV  (
    .I(\counter<19>/TORGTS ),
    .O(\counter<19>/ENABLE )
  );
  X_TRI counter_19_OBUF (
    .I(\counter<19>/OUTMUX ),
    .CTL(\counter<19>/ENABLE ),
    .O(counter[19])
  );
  X_OPAD \counter<19>/PAD  (
    .PAD(counter[19])
  );
  X_BUF \counter_20/CYINIT_4  (
    .I(Madd__n0001_inst_cy_17),
    .O(\counter_20/CYINIT )
  );
  X_INV \counter_20/SRMUX  (
    .I(reset_IBUF),
    .O(\counter_20/SRMUX_OUTPUTNOT )
  );
  X_XOR2 Madd__n0001_inst_sum_19 (
    .I0(Madd__n0001_inst_cy_18),
    .I1(\counter_20/GROM ),
    .O(_n0001[19])
  );
  X_MUX2 Madd__n0001_inst_cy_19_5 (
    .IA(\counter_20/LOGIC_ZERO ),
    .IB(Madd__n0001_inst_cy_18),
    .SEL(\counter_20/GROM ),
    .O(\counter_20/CYMUXG )
  );
  X_BUF \counter_20/COUTUSED  (
    .I(\counter_20/CYMUXG ),
    .O(Madd__n0001_inst_cy_19)
  );
  defparam \counter_20/G .INIT = 16'hF0F0;
  X_LUT4 \counter_20/G  (
    .ADR0(VCC),
    .ADR1(VCC),
    .ADR2(counter_21),
    .ADR3(VCC),
    .O(\counter_20/GROM )
  );
  defparam \counter_20/F .INIT = 16'hCCCC;
  X_LUT4 \counter_20/F  (
    .ADR0(VCC),
    .ADR1(counter_20),
    .ADR2(VCC),
    .ADR3(VCC),
    .O(\counter_20/FROM )
  );
  X_XOR2 Madd__n0001_inst_sum_18 (
    .I0(\counter_20/CYINIT ),
    .I1(\counter_20/FROM ),
    .O(_n0001[18])
  );
  X_MUX2 Madd__n0001_inst_cy_18_6 (
    .IA(\counter_20/LOGIC_ZERO ),
    .IB(\counter_20/CYINIT ),
    .SEL(\counter_20/FROM ),
    .O(Madd__n0001_inst_cy_18)
  );
  X_ZERO \counter_20/LOGIC_ZERO_7  (
    .O(\counter_20/LOGIC_ZERO )
  );
  X_BUF \counter_18/CYINIT_8  (
    .I(Madd__n0001_inst_cy_15),
    .O(\counter_18/CYINIT )
  );
  X_INV \counter_18/SRMUX  (
    .I(reset_IBUF),
    .O(\counter_18/SRMUX_OUTPUTNOT )
  );
  X_XOR2 Madd__n0001_inst_sum_17 (
    .I0(Madd__n0001_inst_cy_16),
    .I1(\counter_18/GROM ),
    .O(_n0001[17])
  );
  X_MUX2 Madd__n0001_inst_cy_17_9 (
    .IA(\counter_18/LOGIC_ZERO ),
    .IB(Madd__n0001_inst_cy_16),
    .SEL(\counter_18/GROM ),
    .O(\counter_18/CYMUXG )
  );
  X_BUF \counter_18/COUTUSED  (
    .I(\counter_18/CYMUXG ),
    .O(Madd__n0001_inst_cy_17)
  );
  defparam \counter_18/G .INIT = 16'hF0F0;
  X_LUT4 \counter_18/G  (
    .ADR0(VCC),
    .ADR1(VCC),
    .ADR2(counter_19),
    .ADR3(VCC),
    .O(\counter_18/GROM )
  );
  defparam \counter_18/F .INIT = 16'hCCCC;
  X_LUT4 \counter_18/F  (
    .ADR0(VCC),
    .ADR1(counter_18),
    .ADR2(VCC),
    .ADR3(VCC),
    .O(\counter_18/FROM )
  );
  X_XOR2 Madd__n0001_inst_sum_16 (
    .I0(\counter_18/CYINIT ),
    .I1(\counter_18/FROM ),
    .O(_n0001[16])
  );
  X_MUX2 Madd__n0001_inst_cy_16_10 (
    .IA(\counter_18/LOGIC_ZERO ),
    .IB(\counter_18/CYINIT ),
    .SEL(\counter_18/FROM ),
    .O(Madd__n0001_inst_cy_16)
  );
  X_ZERO \counter_18/LOGIC_ZERO_11  (
    .O(\counter_18/LOGIC_ZERO )
  );
  X_BUF \counter_16/CYINIT_12  (
    .I(Madd__n0001_inst_cy_13),
    .O(\counter_16/CYINIT )
  );
  X_INV \counter_16/SRMUX  (
    .I(reset_IBUF),
    .O(\counter_16/SRMUX_OUTPUTNOT )
  );
  X_XOR2 Madd__n0001_inst_sum_15 (
    .I0(Madd__n0001_inst_cy_14),
    .I1(\counter_16/GROM ),
    .O(_n0001[15])
  );
  X_MUX2 Madd__n0001_inst_cy_15_13 (
    .IA(\counter_16/LOGIC_ZERO ),
    .IB(Madd__n0001_inst_cy_14),
    .SEL(\counter_16/GROM ),
    .O(\counter_16/CYMUXG )
  );
  X_BUF \counter_16/COUTUSED  (
    .I(\counter_16/CYMUXG ),
    .O(Madd__n0001_inst_cy_15)
  );
  defparam \counter_16/G .INIT = 16'hCCCC;
  X_LUT4 \counter_16/G  (
    .ADR0(VCC),
    .ADR1(counter_17),
    .ADR2(VCC),
    .ADR3(VCC),
    .O(\counter_16/GROM )
  );
  defparam \counter_16/F .INIT = 16'hCCCC;
  X_LUT4 \counter_16/F  (
    .ADR0(VCC),
    .ADR1(counter_16),
    .ADR2(VCC),
    .ADR3(VCC),
    .O(\counter_16/FROM )
  );
  X_XOR2 Madd__n0001_inst_sum_14 (
    .I0(\counter_16/CYINIT ),
    .I1(\counter_16/FROM ),
    .O(_n0001[14])
  );
  X_MUX2 Madd__n0001_inst_cy_14_14 (
    .IA(\counter_16/LOGIC_ZERO ),
    .IB(\counter_16/CYINIT ),