prescale_counter.npl

来自「Xilinx ISE 官方源代码盘第七章 Part1」· NPL 代码 · 共 22 行

JDF F
// Created by Project Navigator ver 1.0
PROJECT prescale_counter
DESIGN prescale_counter Normal
DEVFAM virtexe
DEVFAMTIME 0
DEVICE xcv100e
DEVICETIME 1039247335
DEVPKG bg352
DEVPKGTIME 1039247275
DEVSPEED -6
DEVSPEEDTIME 0
FLOW XST Verilog
FLOWTIME 0
STIMULUS testbench.tf Normal
MODULE prescale_counter.v
MODSTYLE prescale_counter Normal
[STATUS-ALL]
prescale_counter.postParVerilogSimModel=WARNINGS,1039247566
[STRATEGY-LIST]
Normal=True