prescale_counter.syr

Xilinx ISE 官方源代码盘 第五章

Release 5.1.02i - xst F.25
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.60 s | Elapsed : 0.00 / 0.00 s
 
--> Reading design: prescale_counter.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Low Level Synthesis
  6) Final Report
     6.1) Device utilization summary
     6.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : prescale_counter.prj
Input Format                       : VERILOG
Ignore Synthesis Constraint File   : NO
Verilog Search Path                : 
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : prescale_counter
Output Format                      : NGC
Target Device                      : xcv100e-6bg352

---- Source Options
Top Module Name                    : prescale_counter
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Complex Clock Enable Extraction    : YES
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Criterion             : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Top module area constraint         : 100
Top module allowed area overflow   : 5

---- Other Options
read_cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "prescale_counter.prj"
Compiling include file "prescale_counter.v"
Compiling include file "C:/Xilinx/verilog/src/iSE/unisim_comp.v"
Module <prescale_counter> compiled
No errors in compilation

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analysis of file <prescale_counter.prj> succeeded.
 
 
Analyzing top module <prescale_counter>.
Module <prescale_counter> is correct for synthesis.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <prescale_counter>.
    Related source file is prescale_counter.v.
    Found 32-bit register for signal <counter>.
    Found 2-bit adder for signal <$n0000> created at line 12.
    Found 30-bit adder for signal <$n0001> created at line 19.
    Summary:
	inferred  32 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
Unit <prescale_counter> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 32
  1-bit register                   : 32
# Adders/Subtractors               : 2
  2-bit adder                      : 1
  30-bit adder                     : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Library "C:/Xilinx/data/librtl.xst" Consulted

Optimizing unit <prescale_counter> ...

Mapping all equations...
Loading device for application Xst from file 'v100e.nph' in environment C:/Xilinx.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block prescale_counter, actual ratio is 1.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Output File Name               : prescale_counter.ngr
Top Level Output File Name         : prescale_counter
Output Format                      : NGC
Optimization Criterion             : Speed
Keep Hierarchy                     : NO
Macro Generator                    : macro+

Design Statistics
# IOs                              : 34

Macro Statistics :
# Registers                        : 32
#      1-bit register              : 32
# Adders/Subtractors               : 1
#      30-bit adder                : 1

Cell Usage :
# BELS                             : 95
#      GND                         : 1
#      LUT1                        : 3
#      LUT1_D                      : 1
#      LUT1_L                      : 28
#      LUT2                        : 1
#      LUT2_D                      : 2
#      MUXCY                       : 29
#      VCC                         : 1
#      XORCY                       : 29
# FlipFlops/Latches                : 32
#      FDC                         : 2
#      FDCE                        : 30
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 33
#      IBUF                        : 1
#      OBUF                        : 32
=========================================================================

Device utilization summary:
---------------------------

Selected Device : v100ebg352-6 

 Number of Slices:                      19  out of   1200     1%  
 Number of Slice Flip Flops:            32  out of   2400     1%  
 Number of 4 input LUTs:                35  out of   2400     1%  
 Number of bonded IOBs:                 33  out of    200    16%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 32    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 6.043ns (Maximum Frequency: 165.481MHz)
   Minimum input arrival time before clock: 5.802ns
   Maximum output required time after clock: 6.986ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk'
Delay:               6.043ns (Levels of Logic = 31)
  Source:            counter_2
  Destination:       counter_31
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: counter_2 to counter_31
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             2   0.992   1.072  counter_2 (counter_2)
     LUT1_D:I0->LO         1   0.468   0.000  Madd__n0001_inst_lut2_01 (N740)
     MUXCY:S->O            1   0.515   0.000  Madd__n0001_inst_cy_0 (Madd__n0001_inst_cy_0)
     MUXCY:CI->O           1   0.058   0.000  Madd__n0001_inst_cy_1 (Madd__n0001_inst_cy_1)
     MUXCY:CI->O           1   0.058   0.000  Madd__n0001_inst_cy_2 (Madd__n0001_inst_cy_2)
     MUXCY:CI->O           1   0.058   0.000  Madd__n0001_inst_cy_3 (Madd__n0001_inst_cy_3)
     MUXCY:CI->O           1   0.058   0.000  Madd__n0001_inst_cy_4 (Madd__n0001_inst_cy_4)
     MUXCY:CI->O           1   0.058   0.000  Madd__n0001_inst_cy_5 (Madd__n0001_inst_cy_5)
     MUXCY:CI->O           1   0.058   0.000  Madd__n0001_inst_cy_6 (Madd__n0001_inst_cy_6)
     MUXCY:CI->O           1   0.058   0.000  Madd__n0001_inst_cy_7 (Madd__n0001_inst_cy_7)
     MUXCY:CI->O           1   0.058   0.000  Madd__n0001_inst_cy_8 (Madd__n0001_inst_cy_8)
     MUXCY:CI->O           1   0.058   0.000  Madd__n0001_inst_cy_9 (Madd__n0001_inst_cy_9)
     MUXCY:CI->O           1   0.058   0.000  Madd__n0001_inst_cy_10 (Madd__n0001_inst_cy_10)
     MUXCY:CI->O           1   0.058   0.000  Madd__n0001_inst_cy_11 (Madd__n0001_inst_cy_11)
     MUXCY:CI->O           1   0.058   0.000  Madd__n0001_inst_cy_12 (Madd__n0001_inst_cy_12)
     MUXCY:CI->O           1   0.058   0.000  Madd__n0001_inst_cy_13 (Madd__n0001_inst_cy_13)
     MUXCY:CI->O           1   0.058   0.000  Madd__n0001_inst_cy_14 (Madd__n0001_inst_cy_14)
     MUXCY:CI->O           1   0.058   0.000  Madd__n0001_inst_cy_15 (Madd__n0001_inst_cy_15)
     MUXCY:CI->O           1   0.058   0.000  Madd__n0001_inst_cy_16 (Madd__n0001_inst_cy_16)
     MUXCY:CI->O           1   0.058   0.000  Madd__n0001_inst_cy_17 (Madd__n0001_inst_cy_17)
     MUXCY:CI->O           1   0.058   0.000  Madd__n0001_inst_cy_18 (Madd__n0001_inst_cy_18)
     MUXCY:CI->O           1   0.058   0.000  Madd__n0001_inst_cy_19 (Madd__n0001_inst_cy_19)
     MUXCY:CI->O           1   0.058   0.000  Madd__n0001_inst_cy_20 (Madd__n0001_inst_cy_20)
     MUXCY:CI->O           1   0.058   0.000  Madd__n0001_inst_cy_21 (Madd__n0001_inst_cy_21)
     MUXCY:CI->O           1   0.058   0.000  Madd__n0001_inst_cy_22 (Madd__n0001_inst_cy_22)
     MUXCY:CI->O           1   0.058   0.000  Madd__n0001_inst_cy_23 (Madd__n0001_inst_cy_23)
     MUXCY:CI->O           1   0.058   0.000  Madd__n0001_inst_cy_24 (Madd__n0001_inst_cy_24)
     MUXCY:CI->O           1   0.058   0.000  Madd__n0001_inst_cy_25 (Madd__n0001_inst_cy_25)
     MUXCY:CI->O           1   0.058   0.000  Madd__n0001_inst_cy_26 (Madd__n0001_inst_cy_26)
     MUXCY:CI->O           1   0.058   0.000  Madd__n0001_inst_cy_27 (Madd__n0001_inst_cy_27)
     MUXCY:CI->O           0   0.058   0.000  Madd__n0001_inst_cy_28 (Madd__n0001_inst_cy_28)
     XORCY:CI->O           1   0.648   0.000  Madd__n0001_inst_sum_29 (_n0001<29>)
     FDCE:D                    0.724          counter_31
    ----------------------------------------
    Total                      6.043ns (4.971ns logic, 1.072ns route)
                                       (82.3% logic, 17.7% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Offset:              5.802ns (Levels of Logic = 2)
  Source:            reset
  Destination:       counter_7
  Destination Clock: clk rising

  Data Path: reset to counter_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   0.797   0.920  reset_IBUF (reset_IBUF)
     LUT1:I0->O           32   0.468   3.040  counter_30_Aclr_INV1 (counter_30_N84)
     FDCE:CLR                  0.577          counter_7
    ----------------------------------------
    Total                      5.802ns (1.842ns logic, 3.960ns route)
                                       (31.7% logic, 68.3% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Offset:              6.986ns (Levels of Logic = 1)
  Source:            counter_0
  Destination:       counter<0>
  Source Clock:      clk rising

  Data Path: counter_0 to counter<0>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              5   0.992   1.392  counter_0 (counter_0)
     OBUF:I->O                 4.602          counter_0_OBUF (counter<0>)
    ----------------------------------------
    Total                      6.986ns (5.594ns logic, 1.392ns route)
                                       (80.1% logic, 19.9% route)

=========================================================================
CPU : 3.04 / 4.05 s | Elapsed : 3.00 / 4.00 s
 
--> 

Total memory usage is 61868 kilobytes