prescale_counter.twr

Xilinx ISE 官方源代码盘 第五章

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Release 5.1.02i - Trace F.23
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

C:/Xilinx/bin/nt/trce.exe -quiet -e 3 -l 3 -xml prescale_counter
prescale_counter.ncd -o prescale_counter.twr prescale_counter.pcf

Design file:              prescale_counter.ncd
Physical constraint file: prescale_counter.pcf
Device,speed:             xcv100e,-6 (PRODUCTION 1.68 2002-06-19)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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================================================================================
Timing constraint: TS_clk = PERIOD TIMEGRP "clk"  5 nS   HIGH 50.000000 % ;

 63 items analyzed, 0 timing errors detected.
 Minimum period is   4.999ns.
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================================================================================
Timing constraint: TS_upper_counter = MAXDELAY FROM TIMEGRP "upper_counter" TO TIMEGRP 
"upper_counter" TS_clk * 4.000 ;

 465 items analyzed, 0 timing errors detected.
 Maximum delay is   7.507ns.
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================================================================================
Timing constraint: OFFSET = OUT 10 nS  AFTER COMP "clk" ;

 32 items analyzed, 0 timing errors detected.
 Minimum allowable offset is   9.881ns.
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All constraints were met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock clk to Pad
---------------+------------+
               | clk (edge) |
Destination Pad|   to PAD   |
---------------+------------+
counter<0>     |    8.688(R)|
counter<10>    |    8.240(R)|
counter<11>    |    8.764(R)|
counter<12>    |    8.518(R)|
counter<13>    |    8.680(R)|
counter<14>    |    8.663(R)|
counter<15>    |    9.100(R)|
counter<16>    |    9.194(R)|
counter<17>    |    9.242(R)|
counter<18>    |    9.062(R)|
counter<19>    |    8.869(R)|
counter<1>     |    8.818(R)|
counter<20>    |    9.280(R)|
counter<21>    |    9.666(R)|
counter<22>    |    9.522(R)|
counter<23>    |    9.522(R)|
counter<24>    |    9.420(R)|
counter<25>    |    9.446(R)|
counter<26>    |    9.248(R)|
counter<27>    |    9.586(R)|
counter<28>    |    9.881(R)|
counter<29>    |    9.181(R)|
counter<2>     |    9.252(R)|
counter<30>    |    9.706(R)|
counter<31>    |    9.246(R)|
counter<3>     |    8.617(R)|
counter<4>     |    8.738(R)|
counter<5>     |    8.007(R)|
counter<6>     |    8.242(R)|
counter<7>     |    8.449(R)|
counter<8>     |    8.132(R)|
counter<9>     |    8.167(R)|
---------------+------------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    7.507|         |         |         |
---------------+---------+---------+---------+---------+


Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover 560 paths, 0 nets, and 122 connections (87.1% coverage)

Design statistics:
   Minimum period:   7.507ns (Maximum frequency: 133.209MHz)
   Maximum path delay from/to any node:   7.507ns
   Minimum output required time after clock:   9.881ns


Analysis completed Sat Dec 28 11:52:20 2002
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