lib.vhd

Xilinx Ise 官方源代码盘 第四章

package synopsys_attributes is
  -- design compiler constraints and attributes
  attribute ARRIVAL : REAL;
  attribute DONT_TOUCH : BOOLEAN;
  attribute DONT_TOUCH_NETWORK : BOOLEAN;
  attribute DRIVE : REAL;
  attribute EQUAL : BOOLEAN;
  attribute FALL_ARRIVAL : REAL;
  attribute FALL_DRIVE : REAL;
  attribute LOAD : REAL;
  attribute LOGIC_ONE : BOOLEAN;
  attribute LOGIC_ZERO : BOOLEAN;
  attribute MAX_AREA : REAL;
  attribute MAX_DELAY : REAL;
  attribute MAX_FALL_DELAY : REAL;
  attribute MAX_RISE_DELAY : REAL;
  attribute MAX_TRANSITION : REAL;
  attribute MIN_DELAY : REAL;
  attribute MIN_FALL_DELAY : REAL;
  attribute MIN_RISE_DELAY : REAL;
  attribute OPPOSITE : BOOLEAN;
  attribute RISE_ARRIVAL : REAL;
  attribute RISE_DRIVE : REAL;
  attribute UNCONNECTED : BOOLEAN;

  -- state machine attributes
  attribute STATE_VECTOR : STRING;

  -- resource sharing attributes
  subtype resource is integer;
  attribute ADD_OPS : STRING;
  attribute DONT_MERGE_WITH : STRING;
  attribute MAP_TO_MODULE : STRING;
  attribute MAY_MERGE_WITH : STRING;
  attribute OPS : STRING;

  -- general attributes
  attribute ENUM_ENCODING : STRING;
end synopsys_attributes;


package SYNOPSYS is 

  type UNSIGNED is array ( INTEGER range <>) of BIT; 
  type SIGNED is array (INTEGER range <>) of BIT; 
  subtype INT is INTEGER range -1 to 1;
  
  function BIT_OF (R : BOOLEAN) return BIT;
  function "+" ( L : UNSIGNED; R : INT) return UNSIGNED;
  function "+" ( L : UNSIGNED; R : BIT) return UNSIGNED;
  function "-" ( L : UNSIGNED; R : INT) return UNSIGNED;

end SYNOPSYS; 

use WORK.SYNOPSYS.ALL;
package body SYNOPSYS is

  function BIT_OF (R : BOOLEAN) return BIT is
  begin
   case R is
     when TRUE  => return '1';
     when FALSE => return '0';
   end case;
  end;

-------------------------------------------------------------

  function "+" (L : UNSIGNED; R : INT) return UNSIGNED is
    variable CARRY, VALUE : BIT;
    variable RESULT : UNSIGNED(L'LEFT to L'RIGHT);
  begin
    case R is
      when -1 =>     VALUE := '1'; CARRY := '0';
      when  1 =>     VALUE := '0'; CARRY := '1';
      when others => VALUE := '0'; CARRY := '0';
    end case;

    for I in L'RIGHT downto L'LEFT loop  -- L'reverse_range
      RESULT(I) := L(I) xor VALUE xor CARRY;
      CARRY := (L(I) and VALUE) or (L(I) and CARRY) or (CARRY and VALUE);
    end loop;
    return RESULT;
  end;

-------------------------------------------------------------

    function "-" (L : UNSIGNED; R : INT) return UNSIGNED is
    begin
	return L + (-R);
    end;

-------------------------------------------------------------

    function "+" (L : UNSIGNED; R : BIT) return UNSIGNED is
	variable TEMP : INT;
    begin
	if R = '0' then
	    TEMP := 0;
	else
	    TEMP := 1;
	end if;
	return L + TEMP;
    end;
end;


use work.SYNOPSYS.all; 

package AMD_PACK is 

  subtype ADDRESS_SIZE is INTEGER range 1 to 12;
  subtype ADDRESS is UNSIGNED (ADDRESS_SIZE); 
  type ADDRESS_VECTOR is array (INTEGER RANGE <>) of ADDRESS;

  type INSTRUCTION_OPS is (JZ, CJS, JMAP, CJP, PUSH, JSRP, CJV, JRP, RFCT, 
 			   RPCT, CRTN, CJPP, LDCT, LOP, CONT, TWB);  

  type STACK_OPS is (S_NOOP, S_CLEAR, S_POP, S_PUSH); 

  subtype STACK_VECTOR_SIZE is POSITIVE range 1 to 9;
  subtype STACK_VECTOR is BIT_VECTOR( STACK_VECTOR_SIZE); 

  type REGCNT_OPS is (NOOP, LOAD, DEC); 

  type UPC_OPS is (CLEAR, COUNT); 

  type Y_MUX_OPS is (SELECT_DATA, SELECT_REGCNT, SELECT_UPC, SELECT_STACK, 
	             SELECT_NONE);

  function HEX_TO_OP_CODE(HEX_VALUE : UNSIGNED(0 to 3)) return INSTRUCTION_OPS;
  function WIRED_OR(SOURCES: BIT_VECTOR) return bit;
  function WIRED_OR(SOURCES: ADDRESS_VECTOR) return ADDRESS;

end AMD_PACK; 

package body AMD_PACK is

  function HEX_TO_OP_CODE(HEX_VALUE : UNSIGNED(0 to 3)) 
           return INSTRUCTION_OPS is
  begin
    case HEX_VALUE is
      when X"0" => return JZ;
      when X"1" => return CJS;
      when X"2" => return JMAP;
      when X"3" => return CJP;
      when X"4" => return PUSH;
      when X"5" => return JSRP;
      when X"6" => return CJV;
      when X"7" => return JRP;
      when X"8" => return RFCT;
      when X"9" => return RPCT;
      when X"a" => return CRTN;
      when X"b" => return CJPP;
      when X"c" => return LDCT;
      when X"d" => return LOP;
      when X"e" => return CONT;
      when X"f" => return TWB;
    end case;
  end HEX_TO_OP_CODE;

  function WIRED_OR(SOURCES: ADDRESS_VECTOR) return ADDRESS is
    -- pragma resolution_method wired_or
    variable RESOLVED_ADDRESS : ADDRESS;
  begin
    for BIT_INDEX in ADDRESS'LOW to ADDRESS'HIGH loop 
      RESOLVED_ADDRESS(BIT_INDEX) := '0';
      for WORD_INDEX in SOURCES'LEFT to SOURCES'RIGHT loop
	if(SOURCES(WORD_INDEX)(BIT_INDEX) = '1') then
	  RESOLVED_ADDRESS(BIT_INDEX) := '1';
	end if;
      end loop;
    end loop;
    return RESOLVED_ADDRESS;
  end WIRED_OR;

  function WIRED_OR( SOURCES: BIT_VECTOR) return BIT is
    -- pragma resolution_method wired_or
  begin
    for I in SOURCES'LEFT to SOURCES'RIGHT LOOP
      if SOURCES(I) = '1' then return '1'; end if;
    end loop;
    return '0';
  end WIRED_OR;

end AMD_PACK;