control.vhd

Xilinx Ise 官方源代码盘 第四章

library LIB;
use LIB.SYNOPSYS.all; 
use LIB.AMD_PACK.all; 

entity CONTROL is 
  port(INSTRUCTION              : in INSTRUCTION_OPS; 
       CONDITION_CODE           : in BIT; 
       CONDITION_CODE_ENABLE    : in BIT; 
       FORCE_LOAD               : in BIT; 
       REGCNT_ZERO              : in BIT; 
       UPC_CONTROL              : out UPC_OPS;
       STACK_CONTROL            : out STACK_OPS; 
       REGCNT_CONTROL           : out REGCNT_OPS; 
       Y_CONTROL                : out Y_MUX_OPS; 
       PIPELINE_ENABLE          : out BIT; 
       MAPPING_ROM_ENABLE       : out BIT; 
       INTERRUPT_VECTOR_ENABLE  : out BIT); 
end CONTROL ; 

architecture CONTROL_HDL of CONTROL is
begin 

  CONTROL_LOGIC: process (INSTRUCTION,CONDITION_CODE,CONDITION_CODE_ENABLE,
                          FORCE_LOAD,REGCNT_ZERO)
  begin 
    PIPELINE_ENABLE <= '1'; 
    MAPPING_ROM_ENABLE <= '1'; 
    INTERRUPT_VECTOR_ENABLE <= '1'; 
    UPC_CONTROL <= COUNT; 
    STACK_CONTROL <= S_NOOP; 
    Y_CONTROL <= SELECT_UPC; 
    if( FORCE_LOAD = '1') then 
      REGCNT_CONTROL <= NOOP; 
    else 
      REGCNT_CONTROL <= LOAD; 
    end if; 

    case INSTRUCTION is 
      -- Reset: clear stack and upc 
      when JZ => 
        UPC_CONTROL <= CLEAR; 
        STACK_CONTROL <= S_CLEAR; 
        Y_CONTROL <= SELECT_NONE; 
        PIPELINE_ENABLE <= '0'; 
  
      -- Cond jump sub: either jump via data input or just do next inst 
      when CJS =>
        PIPELINE_ENABLE <= '0'; 
        if not (CONDITION_CODE_ENABLE = '0' and CONDITION_CODE = '1') then 
          STACK_CONTROL <= S_PUSH; 
          Y_CONTROL <= SELECT_DATA; 
        end if; 
  
      -- Jump using map:
      when JMAP =>
        MAPPING_ROM_ENABLE <= '0'; 
        Y_CONTROL <= SELECT_DATA; 
  
      -- Cond jump: either jump or next inst
      when CJP =>
        PIPELINE_ENABLE <= '0'; 
        if not (CONDITION_CODE_ENABLE = '0' and CONDITION_CODE = '1') then 
          Y_CONTROL <= SELECT_DATA; 
	end if; 
  
      -- Push stack: stack gets next inst addr, usually as loop setup
      when PUSH =>
        STACK_CONTROL <= S_PUSH; 
        PIPELINE_ENABLE <= '0'; 
        if not (CONDITION_CODE_ENABLE = '0' and CONDITION_CODE = '1') then 
  	  REGCNT_CONTROL <= LOAD; 
        end if; 
  
      -- Push and cond jump sub (2-way) 
      when JSRP =>
        PIPELINE_ENABLE <= '0'; 
        STACK_CONTROL <= S_PUSH; 
        if (CONDITION_CODE_ENABLE = '0' and CONDITION_CODE = '1') then 
  	  Y_CONTROL <= SELECT_REGCNT; 
        else 
          Y_CONTROL <= SELECT_DATA; 
	end if; 
  
      -- Cond junk using vector interrupt
      when CJV =>
        INTERRUPT_VECTOR_ENABLE <= '0'; 
        if not (CONDITION_CODE_ENABLE = '0' and CONDITION_CODE = '1') then 
          Y_CONTROL <= SELECT_DATA; 
	end if; 
        
      -- Cond jump (2-way) 
      when JRP =>
        PIPELINE_ENABLE <= '0'; 
        if (CONDITION_CODE_ENABLE = '0' and CONDITION_CODE = '1') then 
          Y_CONTROL <= SELECT_REGCNT; 
        else
          Y_CONTROL <= SELECT_DATA; 
	end if; 
  
      -- Repeat stack loop if cntr != '0'
      when RFCT =>
        PIPELINE_ENABLE <= '0'; 
        if( REGCNT_ZERO = '0') then 
          Y_CONTROL <= SELECT_STACK; 
  	  REGCNT_CONTROL <= DEC; 
        else 
          STACK_CONTROL <= S_POP; 
        end if; 
  
      -- Repeat D loop is cntr != 0 
      when RPCT =>
        PIPELINE_ENABLE <= '0'; 
        if( REGCNT_ZERO = '0') then 
  	  Y_CONTROL <= SELECT_DATA; 
  	  REGCNT_CONTROL <= DEC; 
        end if; 
  
      -- Conditional return 
      when CRTN =>
        PIPELINE_ENABLE <= '0'; 
        if not (CONDITION_CODE_ENABLE = '0' and CONDITION_CODE = '1') then 
  	  Y_CONTROL <= SELECT_STACK; 
  	  STACK_CONTROL <= S_POP; 
        end if; 
  
      -- Conditional jump and pop       
      when CJPP =>
        PIPELINE_ENABLE <= '0'; 
        if not (CONDITION_CODE_ENABLE = '0' and CONDITION_CODE = '1') then 
  	  Y_CONTROL <= SELECT_DATA; 
  	  STACK_CONTROL <= S_POP; 
        end if; 
        
      -- Load counter/register
      when LDCT =>
        PIPELINE_ENABLE <= '0'; 
        REGCNT_CONTROL <= LOAD; 
  
      -- Test end of loop 
      when LOP =>
        PIPELINE_ENABLE <= '0'; 
        if (CONDITION_CODE_ENABLE = '0' and CONDITION_CODE = '1') then 
  	  Y_CONTROL <= SELECT_STACK; 	-- test failed
        else 
  	  STACK_CONTROL <= S_POP; 	-- end loop and pop 
	end if; 
        
      -- Continue, no-op
      when CONT =>
        PIPELINE_ENABLE <= '0'; 
  
      -- Three-way branch 
      when TWB =>    
        PIPELINE_ENABLE <= '0'; 
        if( REGCNT_ZERO = '0') then 
          REGCNT_CONTROL <= DEC; 
  	  if (CONDITION_CODE_ENABLE = '0' and CONDITION_CODE = '1') then 
  	    Y_CONTROL <= SELECT_STACK; 
  	  else
  	    STACK_CONTROL <= S_POP; 
  	  end if; 
        else
  	  STACK_CONTROL <= S_POP;
  	  if (CONDITION_CODE_ENABLE = '0' and CONDITION_CODE = '1') then 
  	    Y_CONTROL <= SELECT_DATA; 
          end if; 
  	end if; 

    end case; 
  end process CONTROL_LOGIC; 

end CONTROL_HDL;