stack.vhd

Xilinx Ise 官方源代码盘 第四章

library LIB;
use LIB.SYNOPSYS.all; 
use LIB.AMD_PACK.all; 

entity STACK is 
  port(OPERATION    : in STACK_OPS; 
       VALUE        : in ADDRESS; 
       CLOCK        : in BIT; 
       OUTPUT_VALUE : out WIRED_OR ADDRESS; 
       OVERFLOW     : out BIT); 
end STACK; 


architecture STACK_HDL of STACK is 

  -- Tristate latch used to store stack element data 
  component STACK_ELEMENT 
    port(VALUE: in ADDRESS; CLOCK: in BIT; WRITE_ENABLE: in BIT; 
 	 OUTPUT_ENABLE: in BIT; OUTPUT: out ADDRESS); 
  end component; 

  signal WRITE_ENABLE: STACK_VECTOR; 
  signal READ_ENABLE: STACK_VECTOR; 
  signal STACK_TOP, NEW_STACK_TOP : STACK_VECTOR_SIZE;

begin 

  -- Set the write enable mask on if a "push" was requested
  WRITE_EN : process (NEW_STACK_TOP, OPERATION)
  begin 
    WRITE_ENABLE <= STACK_VECTOR'(others => '0');

    if (OPERATION = S_PUSH) then 
      WRITE_ENABLE(NEW_STACK_TOP) <= '1'; 
    end if;   
  end process WRITE_EN;

  -- Set the read enable mask and overflow flag
  READ_EN : process (STACK_TOP)
  begin
    READ_ENABLE <= STACK_VECTOR'(others => '0'); 
    READ_ENABLE(STACK_TOP) <= '1';
    OVERFLOW <= BIT_OF(STACK_TOP = STACK_VECTOR'HIGH);
  end process READ_EN; 

  -- Update the stack top pointer on each clock
  STACK : process
    variable TEMP: INT; 
  begin
    wait until not CLOCK'stable and CLOCK = '1';

    -- Set the top of the stack based on the operation requested
    if (OPERATION = S_CLEAR) then 
      STACK_TOP <= STACK_VECTOR'LOW; 
    else
      if (OPERATION = S_NOOP or
  	  (OPERATION = S_PUSH and STACK_TOP = STACK_VECTOR'HIGH) or
	  (OPERATION = S_POP and STACK_TOP = STACK_VECTOR'LOW)) then 
        TEMP := 0; 
      elsif (OPERATION = S_PUSH) then 
        TEMP := 1; 
      else 
        TEMP := -1; 
      end if; 
      STACK_TOP <= STACK_TOP + TEMP; 
    end if; 
  end process STACK;

    -- Stack values, controlled by read and write enables set above
    U1: STACK_ELEMENT port map(VALUE, CLOCK, WRITE_ENABLE(1), 
  			       READ_ENABLE(1), OUTPUT_VALUE); 
    U2: STACK_ELEMENT port map(VALUE, CLOCK, WRITE_ENABLE(2), 
  			       READ_ENABLE(2), OUTPUT_VALUE); 
    U3: STACK_ELEMENT port map(VALUE, CLOCK, WRITE_ENABLE(3), 
  			       READ_ENABLE(3), OUTPUT_VALUE); 
    U4: STACK_ELEMENT port map(VALUE, CLOCK, WRITE_ENABLE(4), 
  			       READ_ENABLE(4), OUTPUT_VALUE); 
    U5: STACK_ELEMENT port map(VALUE, CLOCK, WRITE_ENABLE(5), 
  			       READ_ENABLE(5), OUTPUT_VALUE); 
    U6: STACK_ELEMENT port map(VALUE, CLOCK, WRITE_ENABLE(6), 
  			       READ_ENABLE(6), OUTPUT_VALUE); 
    U7: STACK_ELEMENT port map(VALUE, CLOCK, WRITE_ENABLE(7), 
  			       READ_ENABLE(7), OUTPUT_VALUE); 
    U8: STACK_ELEMENT port map(VALUE, CLOCK, WRITE_ENABLE(8), 
  			       READ_ENABLE(8), OUTPUT_VALUE); 
    U9: STACK_ELEMENT port map(VALUE, CLOCK, WRITE_ENABLE(9), 
  			       READ_ENABLE(9), OUTPUT_VALUE); 
end STACK_HDL; 


library LIB;
use LIB.SYNOPSYS.all; 
use LIB.AMD_PACK.all; 

-- Latches and tristates an ADDRESS
entity STACK_ELEMENT is 
  port( VALUE: in ADDRESS ; 
	CLOCK: in BIT ; 
	WRITE_ENABLE: in BIT ; 
	OUTPUT_ENABLE: in BIT ; 
	OUTPUT: out ADDRESS) ; 
end STACK_ELEMENT ; 

architecture STACK_ELEMENT_HDL of STACK_ELEMENT is

  -- Tristate element from target library
  component BTS4
    port(A: in BIT; E: in BIT; Z: out BIT) ; 
  end component ; 

  signal GATED_CLOCK: BIT ; 
  signal LATCHED_VALUE : ADDRESS;

begin 

  -- make gated clock for flip-flop
  GATED_CLOCK <= CLOCK and WRITE_ENABLE ;

  -- make flip-flop
  process
  begin 
    wait until (not GATED_CLOCK'stable and GATED_CLOCK = '1') ; 
    LATCHED_VALUE <= VALUE;
  end process ; 

  -- Tristate the output (use tristate components from library)
  U1: BTS4 port map(LATCHED_VALUE(1), OUTPUT_ENABLE, OUTPUT(1));
  U2: BTS4 port map(LATCHED_VALUE(2), OUTPUT_ENABLE, OUTPUT(2)); 
  U3: BTS4 port map(LATCHED_VALUE(3), OUTPUT_ENABLE, OUTPUT(3)); 
  U4: BTS4 port map(LATCHED_VALUE(4), OUTPUT_ENABLE, OUTPUT(4)); 
  U5: BTS4 port map(LATCHED_VALUE(5), OUTPUT_ENABLE, OUTPUT(5)); 
  U6: BTS4 port map(LATCHED_VALUE(6), OUTPUT_ENABLE, OUTPUT(6)); 
  U7: BTS4 port map(LATCHED_VALUE(7), OUTPUT_ENABLE, OUTPUT(7)); 
  U8: BTS4 port map(LATCHED_VALUE(8), OUTPUT_ENABLE, OUTPUT(8)); 
  U9: BTS4 port map(LATCHED_VALUE(9), OUTPUT_ENABLE, OUTPUT(9)); 
  U10: BTS4 port map(LATCHED_VALUE(10), OUTPUT_ENABLE, OUTPUT(10));
  U11: BTS4 port map(LATCHED_VALUE(11), OUTPUT_ENABLE, OUTPUT(11));
  U12: BTS4 port map(LATCHED_VALUE(12), OUTPUT_ENABLE, OUTPUT(12));
end STACK_ELEMENT_HDL ;