cnt_vlog.stx

来自「Xilinx Ise 官方源代码盘 第四章」· STX 代码 · 共 24 行

Release 5.1i - xst F.23
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to .
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=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "cnt_vlog.sprj"
Compiling include file "cnt_vlog.v"
Module <cnt_vlog> compiled
Compiling include file "J:/eda/Xilinx/verilog/src/iSE/unisim_comp.v"
No errors in compilation
Analysis of file <cnt_vlog.sprj> succeeded.

CPU : 0.81 / 1.20 s | Elapsed : 1.00 / 2.00 s
 
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Total memory usage is 52080 kilobytes