cnt_vlog.syr

Xilinx Ise 官方源代码盘 第四章

Release 5.1i - xst F.23
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.
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--> Reading design: cnt_vlog.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Low Level Synthesis
  6) Final Report
     6.1) Device utilization summary
     6.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : cnt_vlog.prj
Input Format                       : VERILOG
Ignore Synthesis Constraint File   : NO
Verilog Search Path                : 
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : cnt_vlog
Output Format                      : NGC
Target Device                      : xc2v40-6cs144

---- Source Options
Top Module Name                    : cnt_vlog
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Complex Clock Enable Extraction    : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 16
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Criterion             : Speed
Optimization Effort                : 2
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : ONLY
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Top module area constraint         : 100
Top module allowed area overflow   : 5

---- Other Options
read_cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "cnt_vlog.prj"
Compiling include file "cnt_vlog.v"
Module <cnt_vlog> compiled
Compiling include file "J:/eda/Xilinx/verilog/src/iSE/unisim_comp.v"
No errors in compilation

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analysis of file <cnt_vlog.prj> succeeded.
 
 
Analyzing top module <cnt_vlog>.
Module <cnt_vlog> is correct for synthesis.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <cnt_vlog>.
    Related source file is cnt_vlog.v.
    Found 16-bit updown counter for signal <COUNT>.
    Summary:
	inferred   1 Counter(s).
Unit <cnt_vlog> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 1
  16-bit updown counter            : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Library "J:/eda/Xilinx/data/librtl.xst" Consulted

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Output File Name               : cnt_vlog.ngr
Keep Hierarchy                     : NO
Macro Generator                    : macro+

Design Statistics
# IOs                              : 37

Cell Usage :
=========================================================================
CPU : 1.46 / 2.06 s | Elapsed : 1.00 / 2.00 s
 
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Total memory usage is 59248 kilobytes