xstdemo_vhdl_prj.npl

Xilinx Ise 官方源代码盘 第四章

JDF F
// Created by Project Navigator ver 1.0
PROJECT XSTDemo_VHDL_prj
DESIGN xstdemo_vhdl_prj Normal
DEVFAM virtex2
DEVFAMTIME 0
DEVICE xc2v40
DEVICETIME 0
DEVPKG cs144
DEVPKGTIME 0
DEVSPEED -6
DEVSPEEDTIME 0
FLOW XST VHDL
FLOWTIME 1038043051
MODULE ..\cnt_vhd.vhd
MODSTYLE cnt_vhd2 Normal
[Normal]
xilxSynthMaxFanout=xstvhd, virtex2, VHDL.t_synthesize, 1038043088, 100
_SynthOptEffort=xstvhd, virtex2, VHDL.t_synthesize, 1038043088, High
[STRATEGY-LIST]
Normal=True