cnt_vhd2.syr

Xilinx Ise 官方源代码盘 第四章

Release 5.1i - xst F.23
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.
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--> Reading design: cnt_vhd2.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Low Level Synthesis
  6) Final Report
     6.1) Device utilization summary
     6.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : cnt_vhd2.prj
Input Format                       : VHDL
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : cnt_vhd2
Output Format                      : NGC
Target Device                      : xc2v40-6cs144

---- Source Options
Entity Name                        : cnt_vhd2
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Complex Clock Enable Extraction    : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 16
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Criterion             : Speed
Optimization Effort                : 2
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : lower
Top module area constraint         : 100
Top module allowed area overflow   : 5

---- Other Options
read_cores                         : YES
cross_clock_analysis               : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file J:/ISE/XST_Demo/VHDL_prj/XSTDemo_VHDL_prj/../cnt_vhd.vhd in Library work.
Architecture behavioral of Entity cnt_vhd2 is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================

Analyzing Entity <cnt_vhd2> (Architecture <behavioral>).
Entity <cnt_vhd2> analyzed. Unit <cnt_vhd2> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <cnt_vhd2>.
    Related source file is J:/ISE/XST_Demo/VHDL_prj/XSTDemo_VHDL_prj/../cnt_vhd.vhd.
    Found 4-bit updown counter for signal <count>.
    Summary:
	inferred   1 Counter(s).
Unit <cnt_vhd2> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 1
  4-bit updown counter             : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Library "J:/eda/Xilinx/data/librtl.xst" Consulted

Optimizing unit <cnt_vhd2> ...

Mapping all equations...
Loading device for application Xst from file '2v40.nph' in environment J:/eda/Xilinx.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block cnt_vhd2, actual ratio is 1.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Output File Name               : cnt_vhd2.ngr
Top Level Output File Name         : cnt_vhd2
Output Format                      : NGC
Optimization Criterion             : Speed
Keep Hierarchy                     : NO
Macro Generator                    : macro+

Design Statistics
# IOs                              : 13

Macro Statistics :
# Counters                         : 1
#      4-bit updown counter        : 1

Cell Usage :
# BELS                             : 17
#      GND                         : 1
#      LUT1                        : 1
#      LUT2                        : 1
#      LUT4_L                      : 4
#      MULT_AND                    : 3
#      MUXCY                       : 3
#      XORCY                       : 4
# FlipFlops/Latches                : 4
#      FDCPE                       : 4
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 12
#      IBUF                        : 8
#      OBUF                        : 4
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2v40cs144-6 

 Number of Slices:                       3  out of    256     1%  
 Number of Slice Flip Flops:             4  out of    512     0%  
 Number of 4 input LUTs:                 6  out of    512     1%  
 Number of bonded IOBs:                 12  out of     88    13%  
 Number of GCLKs:                        1  out of     16     6%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 4     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 3.020ns (Maximum Frequency: 331.126MHz)
   Minimum input arrival time before clock: 4.389ns
   Maximum output required time after clock: 6.173ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk'
Delay:               3.020ns (Levels of Logic = 5)
  Source:            count_0
  Destination:       count_3
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: count_0 to count_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:c->q            2   0.449   0.605  count_0 (count_0)
     LUT4_L:I1->LO         1   0.347   0.000  count_inst_lut4_01 (count_inst_lut4_0)
     MUXCY:s->o            1   0.235   0.000  count_inst_cy_1 (count_inst_cy_1)
     MUXCY:ci->o           1   0.042   0.000  count_inst_cy_2 (count_inst_cy_2)
     MUXCY:ci->o           0   0.042   0.000  count_inst_cy_3 (count_inst_cy_3)
     XORCY:ci->o           1   1.007   0.000  count_inst_sum_3 (count_inst_sum_3)
     FDCPE:d                   0.293          count_3
    ----------------------------------------
    Total                      3.020ns (2.415ns logic, 0.605ns route)
                                       (80.0% logic, 20.0% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Offset:              4.389ns (Levels of Logic = 7)
  Source:            load
  Destination:       count_3
  Destination Clock: clk rising

  Data Path: load to count_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:i->o             2   0.653   0.605  load_ibuf (load_ibuf)
     LUT1:i0->o            4   0.347   0.818  count_inst_lut1_01 (count_inst_lut1_0)
     LUT4_L:I0->LO         1   0.347   0.000  count_inst_lut4_01 (count_inst_lut4_0)
     MUXCY:s->o            1   0.235   0.000  count_inst_cy_1 (count_inst_cy_1)
     MUXCY:ci->o           1   0.042   0.000  count_inst_cy_2 (count_inst_cy_2)
     MUXCY:ci->o           0   0.042   0.000  count_inst_cy_3 (count_inst_cy_3)
     XORCY:ci->o           1   1.007   0.000  count_inst_sum_3 (count_inst_sum_3)
     FDCPE:d                   0.293          count_3
    ----------------------------------------
    Total                      4.389ns (2.966ns logic, 1.423ns route)
                                       (67.6% logic, 32.4% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Offset:              6.173ns (Levels of Logic = 1)
  Source:            count_0
  Destination:       count<0>
  Source Clock:      clk rising

  Data Path: count_0 to count<0>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:c->q            2   0.449   0.605  count_0 (count_0)
     OBUF:i->o                 5.119          count_0_obuf (count<0>)
    ----------------------------------------
    Total                      6.173ns (5.568ns logic, 0.605ns route)
                                       (90.2% logic, 9.8% route)

=========================================================================
CPU : 1.56 / 2.25 s | Elapsed : 2.00 / 2.00 s
 
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