cnt_vhd.vhd

Xilinx Ise 官方源代码盘 第四章

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity cnt_vhd2 is
    Port ( CLK : in std_logic;
           RESET : in std_logic;
           CE : in std_logic;
           LOAD : in std_logic;
           DIR : in std_logic;
           DIN : in std_logic_vector(3 downto 0);
           COUNT : inout std_logic_vector(3 downto 0));
end cnt_vhd2;

architecture Behavioral of cnt_vhd2 is

begin

process (CLK, RESET) 
begin
   if RESET='1' then 
      COUNT <= "0000";
   elsif CLK='1' and CLK'event then
      if CE='1' then
         if LOAD='1' then
      	   COUNT <= DIN;
         else 
            if DIR='1' then  
               COUNT <= COUNT + 1;
            else
               COUNT <= COUNT - 1;
            end if;
         end if;
      end if;
   end if;
end process;
end Behavioral;