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📄 hdl_demo.srr

📁 Xilinx Ise 官方源代码盘 第四章
💻 SRR
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start_value[15]     hdl_demo|clk (rising)     0.000          0.000       -8.434       -8.434 
start_value[16]     hdl_demo|clk (rising)     0.000          0.000       -8.434       -8.434 
start_value[17]     hdl_demo|clk (rising)     0.000          0.000       -8.434       -8.434 
start_value[18]     hdl_demo|clk (rising)     0.000          0.000       -8.434       -8.434 
start_value[19]     hdl_demo|clk (rising)     0.000          0.000       -8.434       -8.434 
start_value[20]     hdl_demo|clk (rising)     0.000          0.000       -8.434       -8.434 
start_value[21]     hdl_demo|clk (rising)     0.000          0.000       -8.434       -8.434 
start_value[22]     hdl_demo|clk (rising)     0.000          0.000       -8.434       -8.434 
start_value[23]     hdl_demo|clk (rising)     0.000          0.000       -8.434       -8.434 
start_value[24]     hdl_demo|clk (rising)     0.000          0.000       -8.434       -8.434 
start_value[25]     hdl_demo|clk (rising)     0.000          0.000       -8.434       -8.434 
start_value[26]     hdl_demo|clk (rising)     0.000          0.000       -8.434       -8.434 
start_value[27]     hdl_demo|clk (rising)     0.000          0.000       -8.434       -8.434 
start_value[28]     hdl_demo|clk (rising)     0.000          0.000       -8.434       -8.434 
start_value[29]     hdl_demo|clk (rising)     0.000          0.000       -8.434       -8.434 
start_value[30]     hdl_demo|clk (rising)     0.000          0.000       -8.434       -8.434 
start_value[31]     hdl_demo|clk (rising)     0.000          0.000       -8.434       -8.434 
=============================================================================================


Output Ports: 

Port          Starting                  User           Arrival     Required          
Name          Reference                 Constraint     Time        Time         Slack
              Clock                                                                  
-------------------------------------------------------------------------------------
result[0]     hdl_demo|clk (rising)     NA             6.511       6.667        0.156
result[1]     hdl_demo|clk (rising)     NA             6.511       6.667        0.156
result[2]     hdl_demo|clk (rising)     NA             6.511       6.667        0.156
result[3]     hdl_demo|clk (rising)     NA             6.511       6.667        0.156
result[4]     hdl_demo|clk (rising)     NA             6.511       6.667        0.156
result[5]     hdl_demo|clk (rising)     NA             6.511       6.667        0.156
result[6]     hdl_demo|clk (rising)     NA             6.511       6.667        0.156
result[7]     hdl_demo|clk (rising)     NA             6.511       6.667        0.156
=====================================================================================



====================================
Detailed Report for Clock: hdl_demo|clk
====================================



Starting Points with Worst Slack
********************************

                 Starting                                                   Arrival            
Instance         Reference        Type        Pin            Net            Time        Slack  
                 Clock                                                                         
-----------------------------------------------------------------------------------------------
accum_a[7:0]     hdl_demo|clk     Port        accum_a[0]     accum_a[0]     0.000       -16.044
accum_a[7:0]     hdl_demo|clk     Port        accum_a[1]     accum_a[1]     0.000       -16.044
accum_a[7:0]     hdl_demo|clk     Port        accum_a[2]     accum_a[2]     0.000       -16.044
accum_a[7:0]     hdl_demo|clk     Port        accum_a[3]     accum_a[3]     0.000       -16.044
accum_b[7:0]     hdl_demo|clk     Port        accum_b[0]     accum_b[0]     0.000       -16.044
accum_b[7:0]     hdl_demo|clk     Port        accum_b[1]     accum_b[1]     0.000       -16.044
accum_b[7:0]     hdl_demo|clk     Port        accum_b[2]     accum_b[2]     0.000       -16.044
accum_b[7:0]     hdl_demo|clk     Port        accum_b[3]     accum_b[3]     0.000       -16.044
op_code[2]       hdl_demo|clk     FD1P3AX     Q              op_code[2]     13.472      -14.082
op_code[1]       hdl_demo|clk     FD1P3AX     Q              op_code[1]     12.589      -13.198
===============================================================================================


Ending Points with Worst Slack
******************************

                     Starting                                            Required            
Instance             Reference        Type         Pin     Net           Time         Slack  
                     Clock                                                                   
---------------------------------------------------------------------------------------------
alu1_outpio[4]       hdl_demo|clk     OFS1P3DX     D       N_255         7.562        -16.044
alu1_outpio[5]       hdl_demo|clk     OFS1P3DX     D       N_251         7.562        -16.044
alu1_outpio[6]       hdl_demo|clk     OFS1P3DX     D       N_247         7.562        -16.044
alu1_outpio[7]       hdl_demo|clk     OFS1P3DX     D       N_243         7.562        -16.044
alu1_outpio[0]       hdl_demo|clk     OFS1P3DX     D       N_271         7.562        -14.082
alu1_outpio[1]       hdl_demo|clk     OFS1P3DX     D       N_267         7.562        -14.082
alu1_outpio[2]       hdl_demo|clk     OFS1P3DX     D       N_263         7.562        -14.082
alu1_outpio[3]       hdl_demo|clk     OFS1P3DX     D       N_259         7.562        -14.082
start                hdl_demo|clk     FD1S3AX      D       N_290         7.562        -8.434 
state_h.state[3]     hdl_demo|clk     FD1P3AX      D       N_123_i_0     7.562        -7.145 
=============================================================================================



Worst Path Information
***********************


Path information for path number 1: 
    Requested Period:                        6.667
    - Setup time:                            -0.895
    = Required time:                         7.562

    - Propagation time:                      23.606
    = Slack (critical) :                     -16.044

    Number of logic level(s):                5
    Starting point:                          accum_a[7:0] / accum_a[0]
    Ending point:                            alu1_outpio[7] / D
    The start point is clocked by            hdl_demo|clk [rising]
    The end   point is clocked by            hdl_demo|clk [rising] on pin SCLK

Instance / Net                           Pin            Pin               Arrival     No. of    
Name                        Type         Name           Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------
accum_a[7:0]                Port         accum_a[0]     In      0.000     0.000       -         
accum_a[0]                  Net          -              -       -         -           0         
accum_a_pad[0]              IBM          I              In      0.000     0.000       -         
accum_a_pad[0]              IBM          O              Out     5.671     5.671       -         
accum_a_c[0]                Net          -              -       -         -           4         
alu1.un4_outp_1.add3_0      FSUB4        A0             In      0.000     5.671       -         
alu1.un4_outp_1.add3_0      FSUB4        BO             Out     4.882     10.553      -         
alu1.un4_outp_1.CRY3        Net          -              -       -         -           1         
alu1.un4_outp_1.add7_4      FSUB4        BI             In      0.000     10.553      -         
alu1.un4_outp_1.add7_4      FSUB4        S3             Out     4.882     15.435      -         
alu1.un4_outp[7]            Net          -              -       -         -           1         
alu1.outp_8_4_0_a6_3[7]     ORCALUT4     A              In      0.000     15.435      -         
alu1.outp_8_4_0_a6_3[7]     ORCALUT4     Z              Out     4.085     19.520      -         
alu1.N_119                  Net          -              -       -         -           1         
alu1.outp_8_4_0[7]          ORCALUT4     C              In      0.000     19.520      -         
alu1.outp_8_4_0[7]          ORCALUT4     Z              Out     4.085     23.606      -         
N_243                       Net          -              -       -         -           1         
alu1_outpio[7]              OFS1P3DX     D              In      0.000     23.606      -         
================================================================================================


Path information for path number 2: 
    Requested Period:                        6.667
    - Setup time:                            -0.895
    = Required time:                         7.562

    - Propagation time:                      23.606
    = Slack (critical) :                     -16.044

    Number of logic level(s):                5
    Starting point:                          accum_a[7:0] / accum_a[1]
    Ending point:                            alu1_outpio[7] / D
    The start point is clocked by            hdl_demo|clk [rising]
    The end   point is clocked by            hdl_demo|clk [rising] on pin SCLK

Instance / Net                           Pin            Pin               Arrival     No. of    
Name                        Type         Name           Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------
accum_a[7:0]                Port         accum_a[1]     In      0.000     0.000       -         
accum_a[1]                  Net          -              -       -         -           0         
accum_a_pad[1]              IBM          I              In      0.000     0.000       -         
accum_a_pad[1]              IBM          O              Out     5.671     5.671       -         
accum_a_c[1]                Net          -              -       -         -           4         
alu1.un4_outp_1.add3_0      FSUB4        A1             In      0.000     5.671       -         
alu1.un4_outp_1.add3_0      FSUB4        BO             Out     4.882     10.553      -         
alu1.un4_outp_1.CRY3        Net          -              -       -         -           1         
alu1.un4_outp_1.add7_4      FSUB4        BI             In      0.000     10.553      -         
alu1.un4_outp_1.add7_4      FSUB4        S3             Out     4.882     15.435      -         
alu1.un4_outp[7]            Net          -              -       -         -           1         
alu1.outp_8_4_0_a6_3[7]     ORCALUT4     A              In      0.000     15.435      -         
alu1.outp_8_4_0_a6_3[7]     ORCALUT4     Z              Out     4.085     19.520      -         
alu1.N_119                  Net          -              -       -         -           1         
alu1.outp_8_4_0[7]          ORCALUT4     C              In      0.000     19.520      -         
alu1.outp_8_4_0[7]          ORCALUT4     Z              Out     4.085     23.606      -         
N_243                       Net          -              -       -         -           1         
alu1_outpio[7]              OFS1P3DX     D              In      0.000     23.606      -         
================================================================================================


Path information for path number 3: 
    Requested Period:                        6.667
    - Setup time:                            -0.895
    = Required time:                         7.562

    - Propagation time:                      23.606
    = Slack (critical) :                     -16.044

    Number of logic level(s):                5
    Starting point:                          accum_a[7:0] / accum_a[2]
    Ending point:                            alu1_outpio[7] / D

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