det_clock.tlg

Xilinx Ise 官方源代码盘 第四章

Selecting top level module det_clock
Synthesizing module det_clock
@W: CL190 :"C:\prj\cpld_detect_error\syn\det_clock.v":21:0:21:5|Optimizing register bit cnt[2] to a constant 0
@W: CL171 :"C:\prj\cpld_detect_error\syn\det_clock.v":21:0:21:5|Pruning Register bit <2> of cnt[2:0]