det_clock.prf

Xilinx Ise 官方源代码盘 第四章

#
# Logical Preferences generated for Lucent by Synplify 7.3.5, Build 222R.
#

# Period Constraints
FREQUENCY PORT "clk_66M" 1.0 MHz;
# Output Constraints
# Input Constraints

BLOCK ASYNCPATHS;

# End of generated Logical Preferences.