det_clock.srr

Xilinx Ise 官方源代码盘 第四章

$ Start of Compile
#Fri Jul 23 10:39:13 2004

Synplicity Verilog Compiler, version Compilers 2.6.0, Build 102R, built Jan 27 2004
Copyright (C) 1994-2004, Synplicity Inc.  All Rights Reserved

@I::"C:\prj\cpld_detect_error\syn\det_clock.v"
Verilog syntax check successful!
Selecting top level module det_clock
Synthesizing module det_clock
@W: CL190 :"C:\prj\cpld_detect_error\syn\det_clock.v":21:0:21:5|Optimizing register bit cnt[2] to a constant 0
@W: CL171 :"C:\prj\cpld_detect_error\syn\det_clock.v":21:0:21:5|Pruning Register bit <2> of cnt[2:0] 

@END
Process took 0h:0m:0s realtime, 0h:0m:0s cputime
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Synplicity Lattice ORCA FPGA Technology Mapper, version 7.3.5, Build 222R, built Feb  5 2004
Copyright (C) 1994-2004, Synplicity Inc.  All Rights Reserved
Setting fanout limit to 100
Automatic dissolve during optimization of view:work.det_clock(verilog) of un1_cnt_1(PM_ADDC__0_2)
---------------------------------------
Resource Usage Report
Part: 3txx2-7

Register bits: 5 of 2636 (0%)
I/O cells:       4

Details:
FD1S3AX:        3
GSR:            1
IBM:            3
IFS1P3DX:       1
OB6:            1
OFS1P3DX:       1
ORCALUT4:       3
VHI:            1
VLO:            1
Found clock det_clock|clk_66M with period 1000.00ns 


##### START OF TIMING REPORT #####[
# Timing Report written on Fri Jul 23 10:39:14 2004
#


Top view:               det_clock
Requested Frequency:    1.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..

@N: MT197 |Clock constraints cover only FF-to-FF paths associated with the clock..



Performance Summary 
*******************


Worst slack in design: 991.562

                      Requested     Estimated     Requested     Estimated                 Clock        Clock              
Starting Clock        Frequency     Frequency     Period        Period        Slack       Type         Group              
--------------------------------------------------------------------------------------------------------------------------
det_clock|clk_66M     1.0 MHz       118.5 MHz     1000.000      8.438         991.562     inferred     Inferred_clkgroup_0
==========================================================================================================================





Clock Relationships
*******************

Clocks                                |    rise  to  rise     |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
------------------------------------------------------------------------------------------------------------------------------
Starting           Ending             |  constraint  slack    |  constraint  slack  |  constraint  slack  |  constraint  slack
------------------------------------------------------------------------------------------------------------------------------
det_clock|clk_66M  det_clock|clk_66M  |  1000.000    991.562  |  No paths    -      |  No paths    -      |  No paths    -    
==============================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

		No IO constraint found 



====================================
Detailed Report for Clock: det_clock|clk_66M
====================================



Starting Points with Worst Slack
********************************

             Starting                                              Arrival            
Instance     Reference             Type         Pin     Net        Time        Slack  
             Clock                                                                    
--------------------------------------------------------------------------------------
cnt[0]       det_clock|clk_66M     FD1S3AX      Q       cnt[0]     5.247       991.562
cnt[1]       det_clock|clk_66M     FD1S3AX      Q       cnt[1]     5.247       991.562
d1_0io       det_clock|clk_66M     IFS1P3DX     Q       d1         5.247       991.562
d2           det_clock|clk_66M     FD1S3AX      Q       d2         4.603       992.206
======================================================================================


Ending Points with Worst Slack
******************************

             Starting                                                Required            
Instance     Reference             Type         Pin     Net          Time         Slack  
             Clock                                                                       
-----------------------------------------------------------------------------------------
cnt[0]       det_clock|clk_66M     FD1S3AX      D       N_10_i_0     1000.895     991.562
cnt[1]       det_clock|clk_66M     FD1S3AX      D       N_12_i_0     1000.895     991.562
err_0io      det_clock|clk_66M     OFS1P3DX     D       err13        1000.895     991.562
d2           det_clock|clk_66M     FD1S3AX      D       d1           997.651      992.404
=========================================================================================



Worst Path Information
***********************


Path information for path number 1: 
    Requested Period:                        1000.000
    - Setup time:                            -0.895
    = Required time:                         1000.895

    - Propagation time:                      9.333
    = Slack (critical) :                     991.562

    Number of logic level(s):                1
    Starting point:                          cnt[0] / Q
    Ending point:                            cnt[0] / D
    The start point is clocked by            det_clock|clk_66M [rising] on pin CK
    The end   point is clocked by            det_clock|clk_66M [rising] on pin CK

Instance / Net                  Pin      Pin               Arrival     No. of    
Name               Type         Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------
cnt[0]             FD1S3AX      Q        Out     5.247     5.247       -         
cnt[0]             Net          -        -       -         -           3         
cnt_6_i[0]         ORCALUT4     B        In      0.000     5.247       -         
cnt_6_i[0]         ORCALUT4     Z        Out     4.085     9.333       -         
N_10_i_0           Net          -        -       -         -           1         
cnt[0]             FD1S3AX      D        In      0.000     9.333       -         
=================================================================================



##### END OF TIMING REPORT #####]


Mapper successful!
Process took 0h:0m:0s realtime, 0h:0m:0s cputime
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