📄 xc4000.vhd
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end component;
component OFDI_FU
port(
Q : out STD_LOGIC;
C : in STD_LOGIC;
D : in STD_LOGIC
);
end component;
----- Component OFDT -----
component OFDT
port(
O : out STD_LOGIC;
C : in STD_LOGIC;
D : in STD_LOGIC;
T : in STD_LOGIC
);
end component;
attribute black_box_tri_pins of OFDT : component is "O";
component OFDT_F
port(
O : out STD_LOGIC;
C : in STD_LOGIC;
D : in STD_LOGIC;
T : in STD_LOGIC
);
end component;
attribute black_box_tri_pins of OFDT_F : component is "O";
component OFDT_S
port(
O : out STD_LOGIC;
C : in STD_LOGIC;
D : in STD_LOGIC;
T : in STD_LOGIC
);
end component;
attribute black_box_tri_pins of OFDT_S : component is "O";
component OFDT_MF
port(
O : out STD_LOGIC;
C : in STD_LOGIC;
D : in STD_LOGIC;
T : in STD_LOGIC
);
end component;
attribute black_box_tri_pins of OFDT_MF : component is "O";
component OFDT_MS
port(
O : out STD_LOGIC;
C : in STD_LOGIC;
D : in STD_LOGIC;
T : in STD_LOGIC
);
end component;
attribute black_box_tri_pins of OFDT_MS : component is "O";
component OFDT_U
port(
O : out STD_LOGIC;
C : in STD_LOGIC;
D : in STD_LOGIC;
T : in STD_LOGIC
);
end component;
attribute black_box_tri_pins of OFDT_U : component is "O";
----- Component OFDTI -----
component OFDTI
port(
O : out STD_LOGIC;
C : in STD_LOGIC;
D : in STD_LOGIC;
T : in STD_LOGIC
);
end component;
attribute black_box_tri_pins of OFDTI : component is "O";
component OFDTI_F
port(
O : out STD_LOGIC;
C : in STD_LOGIC;
D : in STD_LOGIC;
T : in STD_LOGIC
);
end component;
attribute black_box_tri_pins of OFDTI_F : component is "O";
component OFDTI_S
port(
O : out STD_LOGIC;
C : in STD_LOGIC;
D : in STD_LOGIC;
T : in STD_LOGIC
);
end component;
attribute black_box_tri_pins of OFDTI_S : component is "O";
component OFDTI_U
port(
O : out STD_LOGIC;
C : in STD_LOGIC;
D : in STD_LOGIC;
T : in STD_LOGIC
);
end component;
attribute black_box_tri_pins of OFDTI_U : component is "O";
component OFDTI_MF
port(
O : out STD_LOGIC;
C : in STD_LOGIC;
D : in STD_LOGIC;
T : in STD_LOGIC
);
end component;
attribute black_box_tri_pins of OFDTI_MF : component is "O";
component OFDTI_MS
port(
O : out STD_LOGIC;
C : in STD_LOGIC;
D : in STD_LOGIC;
T : in STD_LOGIC
);
end component;
attribute black_box_tri_pins of OFDTI_MS : component is "O";
----- Component OR2 -----
component OR2
port(
O : out STD_LOGIC;
I1 : in STD_LOGIC;
I0 : in STD_LOGIC);
end component;
----- Component OR3 -----
component OR3
port(
O : out STD_LOGIC;
I2 : in STD_LOGIC;
I1 : in STD_LOGIC;
I0 : in STD_LOGIC);
end component;
----- Component OR4 -----
component OR4
port(
O : out STD_LOGIC;
I3 : in STD_LOGIC;
I2 : in STD_LOGIC;
I1 : in STD_LOGIC;
I0 : in STD_LOGIC);
end component;
----- Component OR5 -----
component OR5
port(
O : out STD_LOGIC;
I4 : in STD_LOGIC;
I3 : in STD_LOGIC;
I2 : in STD_LOGIC;
I1 : in STD_LOGIC;
I0 : in STD_LOGIC);
end component;
----- Component OSC4 -----
component OSC4
port(
F8M, F500K, F16K, F490, F15 : out STD_LOGIC
);
end component;
attribute syn_noprune of OSC4 : component is true;
----- Component PULLDOWN -----
component PULLDOWN
port(
O : out STD_LOGIC := 'L');
end component;
attribute syn_noprune of PULLDOWN : component is true;
component PULLDOWN1
port(
O : out STD_LOGIC := 'L');
end component;
attribute syn_black_box of PULLDOWN1: component is false;
----- Component PULLUP -----
component PULLUP
port(
O : out STD_LOGIC := 'H');
end component;
attribute syn_noprune of PULLUP : component is true;
component PULLUP1
port(
O : out STD_LOGIC := 'H');
end component;
attribute syn_black_box of PULLUP1: component is false;
----- Component RAM16X1 ----
component RAM16X1
generic (INIT : bit_vector := X"0000");
port(
O : out STD_LOGIC;
A0, A1, A2, A3, D, WE : in STD_LOGIC
);
end component;
---- Component RAM32X1 ----
component RAM32X1
generic (INIT : bit_vector := X"00000000");
port(
O : out STD_LOGIC;
A0, A1, A2, A3, A4, D, WE : in STD_LOGIC
);
end component;
----- Component RAM16X1D ----
component RAM16X1D
generic (INIT : bit_vector := X"0000");
port(
DPO,SPO : out STD_LOGIC;
DPRA3,DPRA2,DPRA1,DPRA0 : in STD_LOGIC;
A0, A1, A2, A3, D, WE , WCLK : in STD_LOGIC
);
end component;
----- Component RDBK -----
component RDBK
port(
DATA : out STD_LOGIC;
RIP : out STD_LOGIC;
TRIG : in STD_LOGIC);
end component;
component READBACK
port(
DATA : out STD_LOGIC;
RIP : out STD_LOGIC;
CLK : in STD_LOGIC;
TRIG : in STD_LOGIC);
end component;
component RDCLK
port(
I : in STD_LOGIC
);
end component;
attribute syn_noprune of RDCLK : component is true;
----- Component ROM16X1 ----
component ROM16X1
generic (INIT : bit_vector := X"0000");
port(
O : out STD_LOGIC;
A0, A1, A2, A3 : in STD_LOGIC
);
end component;
---- Component ROM32X1 ----
component ROM32X1
generic (INIT : bit_vector := X"00000000");
port(
O : out STD_LOGIC;
A0, A1, A2, A3, A4 : in STD_LOGIC
);
end component;
component STARTUP
port(Q2, Q3, Q1Q4, DONEIN : out std_logic;
GSR, GTS, CLK: in std_logic);
end component;
component STARTUP_GTS
port(GTS: in std_logic);
end component;
attribute syn_noprune of STARTUP_GTS: component is true;
attribute xc_alias of STARTUP_GTS : component is "STARTUP";
component STARTUP_GSR
port(GSR: in std_logic);
end component;
attribute syn_noprune of STARTUP_GSR: component is true;
attribute xc_alias of STARTUP_GSR : component is "STARTUP";
component STARTUP_CLK
port(Q2,Q3,Q1Q4,DONEIN: out std_logic;
CLK: in std_logic);
end component;
attribute syn_noprune of STARTUP_CLK: component is true;
attribute xc_alias of STARTUP_CLK: component is "STARTUP";
component STARTUP_ALL
port(Q2,Q3,Q1Q4,DONEIN: out std_logic;
GSR,GTS,CLK: in std_logic);
end component;
attribute syn_noprune of STARTUP_ALL: component is true;
attribute xc_alias of STARTUP_ALL: component is "STARTUP";
----- Component WAND1 -----
component WAND1
port(
O : out STD_LOGIC;
I : in STD_LOGIC);
end component;
attribute black_box_tri_pins of WAND1 : component is "O";
----- Component WOR2AND -----
component WOR2AND
port(
O : out STD_LOGIC;
I1 : in STD_LOGIC;
I0 : in STD_LOGIC);
end component;
----- Component XGND -----
component XGND
port(
GROUND : out STD_LOGIC
);
end component;
attribute syn_noprune of XGND : component is true;
----- Component XNOR2 -----
component XNOR2
port(
O : out STD_LOGIC;
I1 : in STD_LOGIC;
I0 : in STD_LOGIC);
end component;
----- Component XNOR3 -----
component XNOR3
port(
O : out STD_LOGIC;
I2 : in STD_LOGIC;
I1 : in STD_LOGIC;
I0 : in STD_LOGIC);
end component;
----- Component XNOR4 -----
component XNOR4
port(
O : out STD_LOGIC;
I3 : in STD_LOGIC;
I2 : in STD_LOGIC;
I1 : in STD_LOGIC;
I0 : in STD_LOGIC);
end component;
----- Component XNOR5 -----
component XNOR5
port(
O : out STD_LOGIC;
I4 : in STD_LOGIC;
I3 : in STD_LOGIC;
I2 : in STD_LOGIC;
I1 : in STD_LOGIC;
I0 : in STD_LOGIC);
end component;
----- Component XOR2 -----
component XOR2
port(
O : out STD_LOGIC;
I1 : in STD_LOGIC;
I0 : in STD_LOGIC);
end component;
----- Component XOR3 -----
component XOR3
port(
O : out STD_LOGIC;
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