📄 xc4000.vhd
字号:
C3 : out STD_LOGIC := '0';
C2 : out STD_LOGIC := '0';
C1 : out STD_LOGIC := '0';
C0 : out STD_LOGIC := '0');
end component;
attribute syn_noprune of cy4_38 : component is true;
----- Component cy4_39 -----
component cy4_39
port(
C7 : out STD_LOGIC := '0';
C6 : out STD_LOGIC := '0';
C5 : out STD_LOGIC := '1';
C4 : out STD_LOGIC := '1';
C3 : out STD_LOGIC := '0';
C2 : out STD_LOGIC := '0';
C1 : out STD_LOGIC := '0';
C0 : out STD_LOGIC := '0');
end component;
attribute syn_noprune of cy4_39 : component is true;
----- Component cy4_40 -----
component cy4_40
port(
C7 : out STD_LOGIC := '0';
C6 : out STD_LOGIC := '0';
C5 : out STD_LOGIC := '0';
C4 : out STD_LOGIC := '0';
C3 : out STD_LOGIC := '0';
C2 : out STD_LOGIC := '1';
C1 : out STD_LOGIC := '0';
C0 : out STD_LOGIC := '0');
end component;
attribute syn_noprune of cy4_40 : component is true;
----- Component cy4_41 -----
component cy4_41
port(
C7 : out STD_LOGIC := '0';
C6 : out STD_LOGIC := '0';
C5 : out STD_LOGIC := '1';
C4 : out STD_LOGIC := '0';
C3 : out STD_LOGIC := '0';
C2 : out STD_LOGIC := '0';
C1 : out STD_LOGIC := '0';
C0 : out STD_LOGIC := '0');
end component;
attribute syn_noprune of cy4_41 : component is true;
----- Component cy4_42 -----
component cy4_42
port(
C7 : out STD_LOGIC := '0';
C6 : out STD_LOGIC := '0';
C5 : out STD_LOGIC := '0';
C4 : out STD_LOGIC := '0';
C3 : out STD_LOGIC := '0';
C2 : out STD_LOGIC := '1';
C1 : out STD_LOGIC := '0';
C0 : out STD_LOGIC := '0');
end component;
attribute syn_noprune of cy4_42 : component is true;
----- Component FDCE -----
component FDCE
port(
Q : out STD_LOGIC;
D : in STD_LOGIC;
C : in STD_LOGIC;
CE : in STD_LOGIC;
CLR : in STD_LOGIC
);
end component;
----- Component FDC -----
component FDC
port(
Q : out STD_LOGIC;
D : in STD_LOGIC;
C : in STD_LOGIC;
CLR : in STD_LOGIC
);
end component;
----- Component FDPE -----
component FDPE
port(
Q : out STD_LOGIC;
D : in STD_LOGIC;
C : in STD_LOGIC;
CE : in STD_LOGIC;
PRE : in STD_LOGIC
);
end component;
----- Component FDP -----
component FDP
port(
Q : out STD_LOGIC;
D : in STD_LOGIC;
C : in STD_LOGIC;
PRE : in STD_LOGIC
);
end component;
----- Component FMAP -----
component FMAP
port(
O : out STD_LOGIC;
I1,I2,I3,I4 : in STD_LOGIC
);
end component;
component FMAP_PUC
port(
O : out STD_LOGIC;
I1,I2,I3,I4 : in STD_LOGIC
);
end component;
component FMAP_PLC
port(
O : out STD_LOGIC;
I1,I2,I3,I4 : in STD_LOGIC
);
end component;
component FMAP_PUO
port(
O : out STD_LOGIC;
I1,I2,I3,I4 : in STD_LOGIC
);
end component;
component FMAP_PLO
port(
O : out STD_LOGIC;
I1,I2,I3,I4 : in STD_LOGIC
);
end component;
---- Component HMAP ----
component HMAP
port(
O : out STD_LOGIC;
I1, I2, I3 : in STD_LOGIC
);
end component;
component HMAP_PUC
port(
O : out STD_LOGIC;
I1, I2, I3 : in STD_LOGIC
);
end component;
----- Component IBUF -----
component IBUF
port(
O : out STD_LOGIC;
I : in STD_LOGIC);
end component;
component IBUF_U
port(
O : out STD_LOGIC;
I : in STD_LOGIC);
end component;
component IBUF_CMOS
port(
O : out STD_LOGIC;
I : in STD_LOGIC);
end component;
component IBUF_TTL
port(
O : out STD_LOGIC;
I : in STD_LOGIC);
end component;
----- Component IFD -----
component IFD
port(
Q : out STD_LOGIC;
C : in STD_LOGIC;
D : in STD_LOGIC
);
end component;
component IFD_F
port(
Q : out STD_LOGIC;
C : in STD_LOGIC;
D : in STD_LOGIC
);
end component;
component IFD_U
port(
Q : out STD_LOGIC;
C : in STD_LOGIC;
D : in STD_LOGIC
);
end component;
----- Component IFDI -----
component IFDI
port(
Q : out STD_LOGIC;
C : in STD_LOGIC;
D : in STD_LOGIC
);
end component;
component IFDX
port(
Q : out STD_LOGIC;
C : in STD_LOGIC;
CE : in STD_LOGIC;
D : in STD_LOGIC
);
end component;
component IFDX_F
port(
Q : out STD_LOGIC;
C : in STD_LOGIC;
CE : in STD_LOGIC;
D : in STD_LOGIC
);
end component;
component IFDXI
port(
Q : out STD_LOGIC;
C : in STD_LOGIC;
CE : in STD_LOGIC;
D : in STD_LOGIC
);
end component;
component IFDXI_F
port(
Q : out STD_LOGIC;
C : in STD_LOGIC;
CE : in STD_LOGIC;
D : in STD_LOGIC
);
end component;
component IFDI_F
port(
Q : out STD_LOGIC;
C : in STD_LOGIC;
D : in STD_LOGIC
);
end component;
component IFDI_U
port(
Q : out STD_LOGIC;
C : in STD_LOGIC;
D : in STD_LOGIC
);
end component;
----- Component ILDI_1 -----
component ILDI_1
port(
Q : out STD_LOGIC;
D : in STD_LOGIC;
G : in STD_LOGIC
);
end component;
component ILDI_1F
port(
Q : out STD_LOGIC;
D : in STD_LOGIC;
G : in STD_LOGIC
);
end component;
component ILDI_1U
port(
Q : out STD_LOGIC;
D : in STD_LOGIC;
G : in STD_LOGIC
);
end component;
----- Component ILD_1 -----
component ILD_1
port(
Q : out STD_LOGIC;
D : in STD_LOGIC;
G : in STD_LOGIC
);
end component;
component ILD_1F
port(
Q : out STD_LOGIC;
D : in STD_LOGIC;
G : in STD_LOGIC
);
end component;
component ILD_1U
port(
Q : out STD_LOGIC;
D : in STD_LOGIC;
G : in STD_LOGIC
);
end component;
-- for Spartan-XL and 4000X only
component ILFFX
port(
Q : out STD_LOGIC;
D : in STD_LOGIC;
GF : in STD_LOGIC;
CE : in STD_LOGIC;
C : in STD_LOGIC
);
end component;
-- for Spartan-XL and 4000X only
component ILFFXI
port(
Q : out STD_LOGIC;
D : in STD_LOGIC;
GF : in STD_LOGIC;
CE : in STD_LOGIC;
C : in STD_LOGIC
);
end component;
-- for Spartan-XL and 4000X only
component ILFLX_1
port(
Q : out STD_LOGIC;
D : in STD_LOGIC;
GF : in STD_LOGIC;
GE : in STD_LOGIC;
G : in STD_LOGIC
);
end component;
attribute black_box_pad_pin of ILFLX_1 : component is "D";
-- for Spartan-XL and 4000X only
component ILFLXI_1
port(
Q : out STD_LOGIC;
D : in STD_LOGIC;
GF : in STD_LOGIC;
GE : in STD_LOGIC;
G : in STD_LOGIC
);
end component;
attribute black_box_pad_pin of ILFLXI_1 : component is "D";
-- for Spartan-XL and 4000X only
component ILFLX
port(
Q : out STD_LOGIC;
D : in STD_LOGIC;
GF : in STD_LOGIC;
GE : in STD_LOGIC;
G : in STD_LOGIC
);
end component;
----- Component INV -----
component INV
port(
O : out STD_LOGIC;
I : in STD_LOGIC);
end component;
----- Component PIPEBUF -----
component PIPEBUF
port (
O : out std_logic;
I : in std_logic
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -