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C3 : out STD_LOGIC := '1';
C2 : out STD_LOGIC := '0';
C1 : out STD_LOGIC := '0';
C0 : out STD_LOGIC := '1');
end component;
attribute syn_noprune of cy4_12 : component is true;
----- Component cy4_13 -----
component cy4_13
port(
C7 : out STD_LOGIC := '1';
C6 : out STD_LOGIC := '1';
C5 : out STD_LOGIC := '1';
C4 : out STD_LOGIC := '1';
C3 : out STD_LOGIC := '1';
C2 : out STD_LOGIC := '0';
C1 : out STD_LOGIC := '0';
C0 : out STD_LOGIC := '1');
end component;
attribute syn_noprune of cy4_13 : component is true;
----- Component cy4_14 -----
component cy4_14
port(
C7 : out STD_LOGIC := '1';
C6 : out STD_LOGIC := '1';
C5 : out STD_LOGIC := '1';
C4 : out STD_LOGIC := '1';
C3 : out STD_LOGIC := '0';
C2 : out STD_LOGIC := '0';
C1 : out STD_LOGIC := '0';
C0 : out STD_LOGIC := '1');
end component;
attribute syn_noprune of cy4_14 : component is true;
----- Component cy4_15 -----
component cy4_15
port(
C7 : out STD_LOGIC := '1';
C6 : out STD_LOGIC := '1';
C5 : out STD_LOGIC := '0';
C4 : out STD_LOGIC := '0';
C3 : out STD_LOGIC := '0';
C2 : out STD_LOGIC := '1';
C1 : out STD_LOGIC := '0';
C0 : out STD_LOGIC := '1');
end component;
attribute syn_noprune of cy4_15 : component is true;
----- Component cy4_16 -----
component cy4_16
port(
C7 : out STD_LOGIC := '1';
C6 : out STD_LOGIC := '1';
C5 : out STD_LOGIC := '1';
C4 : out STD_LOGIC := '0';
C3 : out STD_LOGIC := '0';
C2 : out STD_LOGIC := '0';
C1 : out STD_LOGIC := '0';
C0 : out STD_LOGIC := '1');
end component;
attribute syn_noprune of cy4_16 : component is true;
----- Component cy4_17 -----
component cy4_17
port(
C7 : out STD_LOGIC := '0';
C6 : out STD_LOGIC := '0';
C5 : out STD_LOGIC := '1';
C4 : out STD_LOGIC := '1';
C3 : out STD_LOGIC := '1';
C2 : out STD_LOGIC := '0';
C1 : out STD_LOGIC := '1';
C0 : out STD_LOGIC := '0');
end component;
attribute syn_noprune of cy4_17 : component is true;
----- Component cy4_18 -----
component cy4_18
port(
C7 : out STD_LOGIC := '0';
C6 : out STD_LOGIC := '1';
C5 : out STD_LOGIC := '1';
C4 : out STD_LOGIC := '1';
C3 : out STD_LOGIC := '1';
C2 : out STD_LOGIC := '0';
C1 : out STD_LOGIC := '1';
C0 : out STD_LOGIC := '0');
end component;
attribute syn_noprune of cy4_18 : component is true;
----- Component cy4_19 -----
component cy4_19
port(
C7 : out STD_LOGIC := '0';
C6 : out STD_LOGIC := '1';
C5 : out STD_LOGIC := '1';
C4 : out STD_LOGIC := '1';
C3 : out STD_LOGIC := '0';
C2 : out STD_LOGIC := '0';
C1 : out STD_LOGIC := '1';
C0 : out STD_LOGIC := '0');
end component;
attribute syn_noprune of cy4_19 : component is true;
----- Component cy4_20 -----
component cy4_20
port(
C7 : out STD_LOGIC := '0';
C6 : out STD_LOGIC := '1';
C5 : out STD_LOGIC := '0';
C4 : out STD_LOGIC := '0';
C3 : out STD_LOGIC := '0';
C2 : out STD_LOGIC := '0';
C1 : out STD_LOGIC := '0';
C0 : out STD_LOGIC := '0');
end component;
attribute syn_noprune of cy4_20 : component is true;
----- Component cy4_21 -----
component cy4_21
port(
C7 : out STD_LOGIC := '0';
C6 : out STD_LOGIC := '1';
C5 : out STD_LOGIC := '1';
C4 : out STD_LOGIC := '1';
C3 : out STD_LOGIC := '0';
C2 : out STD_LOGIC := '0';
C1 : out STD_LOGIC := '1';
C0 : out STD_LOGIC := '0');
end component;
attribute syn_noprune of cy4_21 : component is true;
----- Component cy4_22 -----
component cy4_22
port(
C7 : out STD_LOGIC := '0';
C6 : out STD_LOGIC := '1';
C5 : out STD_LOGIC := '0';
C4 : out STD_LOGIC := '0';
C3 : out STD_LOGIC := '0';
C2 : out STD_LOGIC := '1';
C1 : out STD_LOGIC := '1';
C0 : out STD_LOGIC := '0');
end component;
attribute syn_noprune of cy4_22 : component is true;
----- Component cy4_23 -----
component cy4_23
port(
C7 : out STD_LOGIC := '0';
C6 : out STD_LOGIC := '1';
C5 : out STD_LOGIC := '1';
C4 : out STD_LOGIC := '0';
C3 : out STD_LOGIC := '0';
C2 : out STD_LOGIC := '0';
C1 : out STD_LOGIC := '1';
C0 : out STD_LOGIC := '0');
end component;
attribute syn_noprune of cy4_23 : component is true;
----- Component cy4_24 -----
component cy4_24
port(
C7 : out STD_LOGIC := '0';
C6 : out STD_LOGIC := '0';
C5 : out STD_LOGIC := '1';
C4 : out STD_LOGIC := '1';
C3 : out STD_LOGIC := '1';
C2 : out STD_LOGIC := '0';
C1 : out STD_LOGIC := '0';
C0 : out STD_LOGIC := '0');
end component;
attribute syn_noprune of cy4_24 : component is true;
----- Component cy4_25 -----
component cy4_25
port(
C7 : out STD_LOGIC := '0';
C6 : out STD_LOGIC := '1';
C5 : out STD_LOGIC := '1';
C4 : out STD_LOGIC := '1';
C3 : out STD_LOGIC := '1';
C2 : out STD_LOGIC := '0';
C1 : out STD_LOGIC := '0';
C0 : out STD_LOGIC := '0');
end component;
attribute syn_noprune of cy4_25 : component is true;
----- Component cy4_26 -----
component cy4_26
port(
C7 : out STD_LOGIC := '0';
C6 : out STD_LOGIC := '1';
C5 : out STD_LOGIC := '1';
C4 : out STD_LOGIC := '1';
C3 : out STD_LOGIC := '0';
C2 : out STD_LOGIC := '0';
C1 : out STD_LOGIC := '0';
C0 : out STD_LOGIC := '0');
end component;
attribute syn_noprune of cy4_26 : component is true;
----- Component cy4_27 -----
component cy4_27
port(
C7 : out STD_LOGIC := '0';
C6 : out STD_LOGIC := '1';
C5 : out STD_LOGIC := '0';
C4 : out STD_LOGIC := '0';
C3 : out STD_LOGIC := '0';
C2 : out STD_LOGIC := '0';
C1 : out STD_LOGIC := '0';
C0 : out STD_LOGIC := '0');
end component;
attribute syn_noprune of cy4_27 : component is true;
----- Component cy4_28 -----
component cy4_28
port(
C7 : out STD_LOGIC := '0';
C6 : out STD_LOGIC := '1';
C5 : out STD_LOGIC := '1';
C4 : out STD_LOGIC := '1';
C3 : out STD_LOGIC := '0';
C2 : out STD_LOGIC := '0';
C1 : out STD_LOGIC := '0';
C0 : out STD_LOGIC := '0');
end component;
attribute syn_noprune of cy4_28 : component is true;
----- Component cy4_29 -----
component cy4_29
port(
C7 : out STD_LOGIC := '0';
C6 : out STD_LOGIC := '1';
C5 : out STD_LOGIC := '0';
C4 : out STD_LOGIC := '0';
C3 : out STD_LOGIC := '0';
C2 : out STD_LOGIC := '1';
C1 : out STD_LOGIC := '0';
C0 : out STD_LOGIC := '0');
end component;
attribute syn_noprune of cy4_29 : component is true;
----- Component cy4_30 -----
component cy4_30
port(
C7 : out STD_LOGIC := '0';
C6 : out STD_LOGIC := '1';
C5 : out STD_LOGIC := '1';
C4 : out STD_LOGIC := '0';
C3 : out STD_LOGIC := '0';
C2 : out STD_LOGIC := '0';
C1 : out STD_LOGIC := '0';
C0 : out STD_LOGIC := '0');
end component;
attribute syn_noprune of cy4_30 : component is true;
----- Component cy4_31 -----
component cy4_31
port(
C7 : out STD_LOGIC := '0';
C6 : out STD_LOGIC := '0';
C5 : out STD_LOGIC := '1';
C4 : out STD_LOGIC := '1';
C3 : out STD_LOGIC := '1';
C2 : out STD_LOGIC := '0';
C1 : out STD_LOGIC := '0';
C0 : out STD_LOGIC := '1');
end component;
attribute syn_noprune of cy4_31 : component is true;
----- Component cy4_32 -----
component cy4_32
port(
C7 : out STD_LOGIC := '0';
C6 : out STD_LOGIC := '1';
C5 : out STD_LOGIC := '1';
C4 : out STD_LOGIC := '1';
C3 : out STD_LOGIC := '1';
C2 : out STD_LOGIC := '0';
C1 : out STD_LOGIC := '0';
C0 : out STD_LOGIC := '1');
end component;
attribute syn_noprune of cy4_32 : component is true;
----- Component cy4_33 -----
component cy4_33
port(
C7 : out STD_LOGIC := '0';
C6 : out STD_LOGIC := '1';
C5 : out STD_LOGIC := '1';
C4 : out STD_LOGIC := '1';
C3 : out STD_LOGIC := '0';
C2 : out STD_LOGIC := '0';
C1 : out STD_LOGIC := '0';
C0 : out STD_LOGIC := '1');
end component;
attribute syn_noprune of cy4_33 : component is true;
----- Component cy4_34 -----
component cy4_34
port(
C7 : out STD_LOGIC := '0';
C6 : out STD_LOGIC := '1';
C5 : out STD_LOGIC := '0';
C4 : out STD_LOGIC := '0';
C3 : out STD_LOGIC := '0';
C2 : out STD_LOGIC := '0';
C1 : out STD_LOGIC := '0';
C0 : out STD_LOGIC := '0');
end component;
attribute syn_noprune of cy4_34 : component is true;
----- Component cy4_35 -----
component cy4_35
port(
C7 : out STD_LOGIC := '0';
C6 : out STD_LOGIC := '1';
C5 : out STD_LOGIC := '1';
C4 : out STD_LOGIC := '1';
C3 : out STD_LOGIC := '0';
C2 : out STD_LOGIC := '0';
C1 : out STD_LOGIC := '0';
C0 : out STD_LOGIC := '1');
end component;
attribute syn_noprune of cy4_35 : component is true;
----- Component cy4_36 -----
component cy4_36
port(
C7 : out STD_LOGIC := '0';
C6 : out STD_LOGIC := '1';
C5 : out STD_LOGIC := '0';
C4 : out STD_LOGIC := '0';
C3 : out STD_LOGIC := '0';
C2 : out STD_LOGIC := '1';
C1 : out STD_LOGIC := '0';
C0 : out STD_LOGIC := '1');
end component;
attribute syn_noprune of cy4_36 : component is true;
----- Component cy4_37 -----
component cy4_37
port(
C7 : out STD_LOGIC := '0';
C6 : out STD_LOGIC := '0';
C5 : out STD_LOGIC := '0';
C4 : out STD_LOGIC := '0';
C3 : out STD_LOGIC := '0';
C2 : out STD_LOGIC := '0';
C1 : out STD_LOGIC := '0';
C0 : out STD_LOGIC := '0');
end component;
attribute syn_noprune of cy4_37 : component is true;
----- Component cy4_38 -----
component cy4_38
port(
C7 : out STD_LOGIC := '1';
C6 : out STD_LOGIC := '0';
C5 : out STD_LOGIC := '0';
C4 : out STD_LOGIC := '0';
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