📄 xc4000.vhd
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-- VHDL Xilinx/xc4000 Import library.
-- Copyright 1995 Synplicity Inc.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package components is
attribute syn_black_box: boolean;
attribute black_box_pad: boolean;
attribute black_box_pad_pin: string;
attribute black_box_tri_pins : string;
attribute \.globalbuf\ : boolean;
attribute xc_alias: string;
attribute xc_props: string;
attribute syn_noprune: boolean;
attribute xc_padmacro : boolean;
attribute syn_black_box of components : package is true;
----- Component AND2 -----
component AND2
port(
O : out STD_LOGIC;
I1 : in STD_LOGIC;
I0 : in STD_LOGIC);
end component;
----- Component AND3 -----
component AND3
port(
O : out STD_LOGIC;
I2 : in STD_LOGIC;
I1 : in STD_LOGIC;
I0 : in STD_LOGIC);
end component;
----- Component AND4 -----
component AND4
port(
O : out STD_LOGIC;
I3 : in STD_LOGIC;
I2 : in STD_LOGIC;
I1 : in STD_LOGIC;
I0 : in STD_LOGIC);
end component;
----- Component AND5 -----
component AND5
port(
O : out STD_LOGIC;
I4 : in STD_LOGIC;
I3 : in STD_LOGIC;
I2 : in STD_LOGIC;
I1 : in STD_LOGIC;
I0 : in STD_LOGIC);
end component;
component TDI
port(
I : out STD_LOGIC);
end component;
component TCK
port(
I : out STD_LOGIC);
end component;
component TMS
port(
I : out STD_LOGIC);
end component;
component TDO
port(
O : in STD_LOGIC);
end component;
attribute syn_noprune of TDO: component is true;
--
-- Note: Port directions are compatable with an M1.5 patch
-- available from Xilinx.
--
component MD0
port (I : out std_logic);
end component;
attribute black_box_pad_pin of MD0 : component is "I";
attribute syn_noprune of MD0: component is true;
component MD2
port (I : out std_logic);
end component;
attribute black_box_pad_pin of MD2 : component is "I";
attribute syn_noprune of MD2: component is true;
component MD1
port (O : in std_logic);
end component;
attribute black_box_pad_pin of MD1 : component is "O";
attribute syn_noprune of MD1: component is true;
----- Component BSCAN -----
component BSCAN
port(
TDO : out STD_LOGIC;
DRCK : out STD_LOGIC;
IDLE : out STD_LOGIC;
SEL1 : out STD_LOGIC;
SEL2 : out STD_LOGIC;
TDI : in STD_LOGIC;
TMS : in STD_LOGIC;
TCK : in STD_LOGIC;
TDO1 : in STD_LOGIC;
TDO2 : in STD_LOGIC);
end component;
----- Component BUF -----
component BUF
port(
O : out STD_LOGIC;
I : in STD_LOGIC);
end component;
----- Component BUFG -----
component BUFG
port(
O : out STD_LOGIC;
I : in STD_LOGIC);
end component;
----- Component BUFGLS -----
component BUFGLS
port(
O : out STD_LOGIC;
I : in STD_LOGIC);
end component;
component BUFG_F
port(
O : out STD_LOGIC;
I : in STD_LOGIC);
end component;
----- Component BUFGP -----
component BUFGP
port(
O : out STD_LOGIC;
I : in STD_LOGIC);
end component;
component BUFGP_F
port(
O : out STD_LOGIC;
I : in STD_LOGIC);
end component;
----- Component BUFGS -----
component BUFGS
port(
O : out STD_LOGIC;
I : in STD_LOGIC);
end component;
component BUFGS_F
port(
O : out STD_LOGIC;
I : in STD_LOGIC);
end component;
----- Component BUFT -----
component BUFT
port(
O : out STD_LOGIC;
I : in STD_LOGIC;
T : in STD_LOGIC);
end component;
attribute syn_black_box of BUFT : component is true;
attribute black_box_tri_pins of BUFT : component is "O";
----- Component CY4 -----
component CY4
port(
COUT : out STD_LOGIC;
COUT0 : out STD_LOGIC;
CIN : in STD_LOGIC;
A0 : in STD_LOGIC;
A1 : in STD_LOGIC;
B0 : in STD_LOGIC;
B1 : in STD_LOGIC;
ADD : in STD_LOGIC;
C0 : in STD_LOGIC;
C1 : in STD_LOGIC;
C2 : in STD_LOGIC;
C3 : in STD_LOGIC;
C4 : in STD_LOGIC;
C5 : in STD_LOGIC;
C6 : in STD_LOGIC;
C7 : in STD_LOGIC);
end component;
----- Component cy4_01 -----
component cy4_01
port(
C7 : out STD_LOGIC := '1';
C6 : out STD_LOGIC := '0';
C5 : out STD_LOGIC := '1';
C4 : out STD_LOGIC := '1';
C3 : out STD_LOGIC := '1';
C2 : out STD_LOGIC := '0';
C1 : out STD_LOGIC := '1';
C0 : out STD_LOGIC := '0');
end component;
attribute syn_noprune of cy4_01 : component is true;
----- Component cy4_02 -----
component cy4_02
port(
C7 : out STD_LOGIC := '1';
C6 : out STD_LOGIC := '1';
C5 : out STD_LOGIC := '1';
C4 : out STD_LOGIC := '1';
C3 : out STD_LOGIC := '1';
C2 : out STD_LOGIC := '0';
C1 : out STD_LOGIC := '1';
C0 : out STD_LOGIC := '0');
end component;
attribute syn_noprune of cy4_02 : component is true;
----- Component cy4_03 -----
component cy4_03
port(
C7 : out STD_LOGIC := '1';
C6 : out STD_LOGIC := '1';
C5 : out STD_LOGIC := '1';
C4 : out STD_LOGIC := '1';
C3 : out STD_LOGIC := '0';
C2 : out STD_LOGIC := '0';
C1 : out STD_LOGIC := '1';
C0 : out STD_LOGIC := '0');
end component;
attribute syn_noprune of cy4_03 : component is true;
----- Component cy4_04 -----
component cy4_04
port(
C7 : out STD_LOGIC := '1';
C6 : out STD_LOGIC := '1';
C5 : out STD_LOGIC := '0';
C4 : out STD_LOGIC := '0';
C3 : out STD_LOGIC := '0';
C2 : out STD_LOGIC := '1';
C1 : out STD_LOGIC := '1';
C0 : out STD_LOGIC := '0');
end component;
attribute syn_noprune of cy4_04 : component is true;
----- Component cy4_05 -----
component cy4_05
port(
C7 : out STD_LOGIC := '1';
C6 : out STD_LOGIC := '1';
C5 : out STD_LOGIC := '1';
C4 : out STD_LOGIC := '0';
C3 : out STD_LOGIC := '0';
C2 : out STD_LOGIC := '0';
C1 : out STD_LOGIC := '1';
C0 : out STD_LOGIC := '0');
end component;
attribute syn_noprune of cy4_05 : component is true;
----- Component cy4_06 -----
component cy4_06
port(
C7 : out STD_LOGIC := '1';
C6 : out STD_LOGIC := '0';
C5 : out STD_LOGIC := '1';
C4 : out STD_LOGIC := '1';
C3 : out STD_LOGIC := '1';
C2 : out STD_LOGIC := '0';
C1 : out STD_LOGIC := '0';
C0 : out STD_LOGIC := '0');
end component;
attribute syn_noprune of cy4_06 : component is true;
----- Component cy4_07 -----
component cy4_07
port(
C7 : out STD_LOGIC := '1';
C6 : out STD_LOGIC := '1';
C5 : out STD_LOGIC := '1';
C4 : out STD_LOGIC := '1';
C3 : out STD_LOGIC := '1';
C2 : out STD_LOGIC := '0';
C1 : out STD_LOGIC := '0';
C0 : out STD_LOGIC := '0');
end component;
attribute syn_noprune of cy4_07 : component is true;
----- Component cy4_08 -----
component cy4_08
port(
C7 : out STD_LOGIC := '1';
C6 : out STD_LOGIC := '1';
C5 : out STD_LOGIC := '0';
C4 : out STD_LOGIC := '0';
C3 : out STD_LOGIC := '0';
C2 : out STD_LOGIC := '0';
C1 : out STD_LOGIC := '0';
C0 : out STD_LOGIC := '0');
end component;
attribute syn_noprune of cy4_08 : component is true;
----- Component cy4_09 -----
component cy4_09
port(
C7 : out STD_LOGIC := '1';
C6 : out STD_LOGIC := '1';
C5 : out STD_LOGIC := '0';
C4 : out STD_LOGIC := '0';
C3 : out STD_LOGIC := '0';
C2 : out STD_LOGIC := '1';
C1 : out STD_LOGIC := '0';
C0 : out STD_LOGIC := '0');
end component;
attribute syn_noprune of cy4_09 : component is true;
----- Component cy4_10 -----
component cy4_10
port(
C7 : out STD_LOGIC := '1';
C6 : out STD_LOGIC := '1';
C5 : out STD_LOGIC := '1';
C4 : out STD_LOGIC := '1';
C3 : out STD_LOGIC := '0';
C2 : out STD_LOGIC := '0';
C1 : out STD_LOGIC := '0';
C0 : out STD_LOGIC := '0');
end component;
attribute syn_noprune of cy4_10 : component is true;
----- Component cy4_11 -----
component cy4_11
port(
C7 : out STD_LOGIC := '1';
C6 : out STD_LOGIC := '1';
C5 : out STD_LOGIC := '1';
C4 : out STD_LOGIC := '0';
C3 : out STD_LOGIC := '0';
C2 : out STD_LOGIC := '0';
C1 : out STD_LOGIC := '0';
C0 : out STD_LOGIC := '0');
end component;
attribute syn_noprune of cy4_11 : component is true;
----- Component cy4_12 -----
component cy4_12
port(
C7 : out STD_LOGIC := '1';
C6 : out STD_LOGIC := '0';
C5 : out STD_LOGIC := '1';
C4 : out STD_LOGIC := '1';
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